71 lines
1.7 KiB
VHDL
71 lines
1.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity alu is
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port(
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a: in std_logic_vector(15 downto 0);
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b: in std_logic_vector(15 downto 0);
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sel: in std_logic_vector(3 downto 0);
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flag: out std_logic;
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q: out std_logic_vector(15 downto 0)
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);
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end alu;
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architecture behavior of alu is
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begin
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process(a, b, sel) is
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variable tmp: std_logic_vector(31 downto 0);
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variable idx: natural;
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begin
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q <= x"0000";
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flag <= '0';
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tmp := x"00000000";
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idx := 0;
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case sel is
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when "0011" => -- q = a + b, flag is carry
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tmp(16 downto 0) := std_logic_vector(unsigned('0' & a) + unsigned(b));
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q <= tmp(15 downto 0);
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flag <= tmp(16);
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when "0100" => -- q = a - b, flag if a < b
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tmp(16 downto 0) := std_logic_vector(unsigned('1' & a) - unsigned(b));
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q <= tmp(15 downto 0);
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flag <= not tmp(16);
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when "0101" => q <= a or b;
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when "0110" => q <= a and b;
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when "0111" => q <= not a;
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when "1000" => q <= a xor b;
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when "1001" => -- left shift by 1
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q <= a(14 downto 0) & '0';
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flag <= a(15);
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when "1010" => -- right shift by b(3 downto 0)
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idx := to_integer(unsigned(b(3 downto 0)));
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tmp(15 - idx downto 0) := a(15 downto idx);
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q <= tmp(15 downto 0);
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flag <= a(0);
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when "1011" => -- q = a * b
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--tmp := std_logic_vector(unsigned(a) * unsigned(b));
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q <= tmp(15 downto 0);
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when "1100" => -- flag if a = b
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if (a = b) then
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flag <= '1';
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else
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flag <= '0';
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end if;
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--- room for a few more things:
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-- - rotate
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-- - not / nand
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-- - gt...
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when others =>
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-- do nothing
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end case;
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end process;
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end behavior;
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