311 lines
9.7 KiB
C
311 lines
9.7 KiB
C
/******************************************************************************
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* Copyright (C) 2002 - 2022 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file xuartlite_l.h
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* @addtogroup uartlite_v3_7
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* @{
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*
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* This header file contains identifiers and low-level driver functions (or
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* macros) that can be used to access the device. High-level driver functions
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* are defined in xuartlite.h.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00b rpm 04/25/02 First release
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* 1.00b rpm 07/07/03 Removed references to XUartLite_GetControlReg macro
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* since the control register is write-only
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* 1.12a mta 03/21/07 Updated to new coding style
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* 1.13a sv 01/21/08 Updated driver to support access through DCR bus
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* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been
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* renamed to remove _m from the name.
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* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
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* Changed the prototypes of XUartLite_SendByte,
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* XUartLite_RecvByte APIs.
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* </pre>
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*
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*****************************************************************************/
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#ifndef XUARTLITE_L_H /* prevent circular inclusions */
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#define XUARTLITE_L_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files ********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/*
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* XPAR_XUARTLITE_USE_DCR_BRIDGE has to be set to 1 if the UartLite device is
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* accessed through a DCR bus connected to a bridge.
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*/
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#define XPAR_XUARTLITE_USE_DCR_BRIDGE 0
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#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
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#include "xio_dcr.h"
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#endif
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/************************** Constant Definitions ****************************/
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/* UART Lite register offsets */
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#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
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#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */
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#define XUL_TX_FIFO_OFFSET 1 /* transmit FIFO, write only */
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#define XUL_STATUS_REG_OFFSET 2 /* status register, read only */
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#define XUL_CONTROL_REG_OFFSET 3 /* control reg, write only */
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#else
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#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */
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#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */
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#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */
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#define XUL_CONTROL_REG_OFFSET 12 /* control reg, write only */
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#endif
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/* Control Register bit positions */
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#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */
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#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */
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#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */
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/* Status Register bit positions */
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#define XUL_SR_PARITY_ERROR 0x80
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#define XUL_SR_FRAMING_ERROR 0x40
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#define XUL_SR_OVERRUN_ERROR 0x20
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#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */
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#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
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#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */
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#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
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#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
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/* The following constant specifies the size of the Transmit/Receive FIFOs.
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* The FIFO size is fixed to 16 in the Uartlite IP and the size is not
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* configurable. This constant is not used in the driver.
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*/
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#define XUL_FIFO_SIZE 16
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/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
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* per instance basis
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*/
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#define XUL_STOP_BITS 1
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/* Parity definitions
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*/
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#define XUL_PARITY_NONE 0
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#define XUL_PARITY_ODD 1
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#define XUL_PARITY_EVEN 2
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/**************************** Type Definitions ******************************/
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/***************** Macros (Inline Functions) Definitions ********************/
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/*
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* Define the appropriate I/O access method to memory mapped I/O or DCR.
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*/
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#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
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#define XUartLite_In32 XIo_DcrIn
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#define XUartLite_Out32 XIo_DcrOut
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#else
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#define XUartLite_In32 Xil_In32
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#define XUartLite_Out32 Xil_Out32
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#endif
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/****************************************************************************/
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/**
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*
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* Write a value to a UartLite register. A 32 bit write is performed.
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*
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* @param BaseAddress is the base address of the UartLite device.
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* @param RegOffset is the register offset from the base to write to.
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* @param Data is the data written to the register.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XUartLite_WriteReg(u32 BaseAddress, u32 RegOffset,
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* u32 Data)
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*
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****************************************************************************/
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#define XUartLite_WriteReg(BaseAddress, RegOffset, Data) \
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XUartLite_Out32((BaseAddress) + (RegOffset), (u32)(Data))
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/****************************************************************************/
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/**
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*
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* Read a value from a UartLite register. A 32 bit read is performed.
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*
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* @param BaseAddress is the base address of the UartLite device.
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* @param RegOffset is the register offset from the base to read from.
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*
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* @return Data read from the register.
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*
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* @note C-style signature:
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* u32 XUartLite_ReadReg(u32 BaseAddress, u32 RegOffset)
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*
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****************************************************************************/
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#define XUartLite_ReadReg(BaseAddress, RegOffset) \
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XUartLite_In32((BaseAddress) + (RegOffset))
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/****************************************************************************/
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/**
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*
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* Set the contents of the control register. Use the XUL_CR_* constants defined
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* above to create the bit-mask to be written to the register.
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*
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* @param BaseAddress is the base address of the device
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* @param Mask is the 32-bit value to write to the control register
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*
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* @return None.
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*
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* @note C-style Signature:
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* void XUartLite_SetControlReg(u32 BaseAddress, u32 Mask);
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*
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*****************************************************************************/
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#define XUartLite_SetControlReg(BaseAddress, Mask) \
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XUartLite_WriteReg((BaseAddress), XUL_CONTROL_REG_OFFSET, (Mask))
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/****************************************************************************/
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/**
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*
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* Get the contents of the status register. Use the XUL_SR_* constants defined
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* above to interpret the bit-mask returned.
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*
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* @param BaseAddress is the base address of the device
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*
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* @return A 32-bit value representing the contents of the status register.
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*
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* @note C-style Signature:
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* u32 XUartLite_GetStatusReg(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XUartLite_GetStatusReg(BaseAddress) \
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XUartLite_ReadReg((BaseAddress), XUL_STATUS_REG_OFFSET)
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/****************************************************************************/
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/**
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*
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* Check to see if the receiver has data.
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*
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* @param BaseAddress is the base address of the device
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*
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* @return TRUE if the receiver is empty, FALSE if there is data present.
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*
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* @note C-style Signature:
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* int XUartLite_IsReceiveEmpty(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XUartLite_IsReceiveEmpty(BaseAddress) \
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((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \
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XUL_SR_RX_FIFO_VALID_DATA)
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/****************************************************************************/
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/**
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*
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* Check to see if the transmitter is full.
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*
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* @param BaseAddress is the base address of the device
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*
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* @return TRUE if the transmitter is full, FALSE otherwise.
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*
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* @note C-style Signature:
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* int XUartLite_IsTransmitFull(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XUartLite_IsTransmitFull(BaseAddress) \
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((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \
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XUL_SR_TX_FIFO_FULL)
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/****************************************************************************/
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/**
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*
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* Check to see if the interrupt is enabled.
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*
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* @param BaseAddress is the base address of the device
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*
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* @return TRUE if the interrupt is enabled, FALSE otherwise.
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*
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* @note C-style Signature:
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* int XUartLite_IsIntrEnabled(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XUartLite_IsIntrEnabled(BaseAddress) \
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((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) == \
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XUL_SR_INTR_ENABLED)
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/****************************************************************************/
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/**
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*
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* Enable the device interrupt. We cannot read the control register, so we
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* just write the enable interrupt bit and clear all others. Since the only
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* other ones are the FIFO reset bits, this works without side effects.
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*
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* @param BaseAddress is the base address of the device
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*
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* @return None.
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*
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* @note C-style Signature:
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* void XUartLite_EnableIntr(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XUartLite_EnableIntr(BaseAddress) \
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XUartLite_SetControlReg((BaseAddress), XUL_CR_ENABLE_INTR)
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/****************************************************************************/
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/**
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*
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* Disable the device interrupt. We cannot read the control register, so we
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* just clear all bits. Since the only other ones are the FIFO reset bits,
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* this works without side effects.
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*
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* @param BaseAddress is the base address of the device
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*
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* @return None.
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*
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* @note C-style Signature:
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* void XUartLite_DisableIntr(u32 BaseAddress);
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*
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*****************************************************************************/
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#define XUartLite_DisableIntr(BaseAddress) \
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XUartLite_SetControlReg((BaseAddress), 0)
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/************************** Function Prototypes *****************************/
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void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data);
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u8 XUartLite_RecvByte(UINTPTR BaseAddress);
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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/** @} */
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