27 lines
404 B
VHDL
27 lines
404 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity dff is
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port(
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clk : in std_logic;
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rst : in std_logic;
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d : in std_logic;
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q : out std_logic
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);
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end entity dff;
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architecture behavior of dff is
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begin
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process(clk, rst) is
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begin
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if (rst = '1') then
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q <= '0';
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else
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if rising_edge(clk) then
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q <= d;
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end if;
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end if;
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end process;
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end architecture behavior;
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