176 lines
4.0 KiB
VHDL
176 lines
4.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- some kind of square wave generator, with PDM output
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entity wave is
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port
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(
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-- AXI4 slave interface
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aclk : in std_logic;
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aresetn : in std_logic;
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-- read addr
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araddr : in std_logic_vector(31 downto 0);
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arvalid : in std_logic;
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arready : out std_logic;
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-- read data
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rdata : out std_logic_vector(31 downto 0);
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rresp : out std_logic;
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rvalid : out std_logic;
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rready : in std_logic;
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-- write addr
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awaddr : in std_logic_vector(31 downto 0);
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awvalid : in std_logic;
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awready : out std_logic;
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-- write data
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wdata : in std_logic_vector(31 downto 0);
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wstrb : in std_logic_vector(3 downto 0);
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-- write resp
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bresp : out std_logic;
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bvalid : out std_logic;
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bready : in std_logic;
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-- PDM output!
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pdmout : out std_logic
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);
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end wave;
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--
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-- Mem layout:
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-- 0x00: control: [bit0: enabled]
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-- 0x04: 32-bit unsigned period (in clock cycles)
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-- 0x08: 16-bit unsigned high value (high 16 bits ignored)
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-- 0x0c: 16-bit unsigned low value (high 16 bits ignored)
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architecture Behavioral of wave is
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component pdm is
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- hardware
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out_pin : out std_logic;
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-- input interface
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enabled : in std_logic;
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sample : in std_logic_vector(15 downto 0)
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);
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end component;
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-- all registers
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signal period, hi_val, lo_val, sample: std_logic_vector(15 downto 0);
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signal enabled, rst, onwrite: std_logic;
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signal counter: unsigned(23 downto 0);
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begin
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arready <= '1';
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awready <= '1';
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rst <= not aresetn;
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pdm0: pdm port map(clk => aclk, rst => rst, out_pin => pdmout,
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sample => sample, enabled => enabled);
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-- main process
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-- drives counter, sample
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process(aclk, aresetn)
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variable high: std_logic;
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begin
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if aresetn = '0' then
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counter <= to_unsigned(0, 24);
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sample <= x"0000";
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high := '0';
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elsif rising_edge(aclk) then
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counter <= to_unsigned(0, 24);
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if high = '1' then
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sample <= hi_val;
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else
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sample <= lo_val;
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end if;
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if enabled = '1' and unsigned(period) /= 0 and onwrite = '0' then
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if counter(22 downto 7) = unsigned(period) - 1
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and counter(6 downto 0) = x"7f" then
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high := not high;
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else
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counter <= counter + 1;
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end if;
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end if;
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end if;
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end process;
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-- Bus slave process
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-- drives period, value, out_addr, enabled, onwrite
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process(aclk, aresetn)
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-- 00: control, 01: period, 02: high, 03: low
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variable waddr: std_logic_vector(2 downto 0);
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variable raddr: std_logic_vector(2 downto 0);
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begin
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if aresetn = '0' then
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period <= x"0000";
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hi_val <= x"0000";
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lo_val <= x"0000";
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enabled <= '0';
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waddr := "000";
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elsif rising_edge(aclk) then
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rvalid <= '0';
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rdata <= x"00000000";
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rresp <= '0';
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bvalid <= '0';
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bresp <= '0';
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onwrite <= '0';
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if arvalid = '1' then
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raddr := araddr(4 downto 2);
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end if;
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if awvalid = '1' then
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waddr := awaddr(4 downto 2);
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end if;
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if arvalid = '1' then
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case waddr(1 downto 0) is
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when "00" =>
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rdata(0) <= enabled;
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when "01" =>
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rdata(23 downto 8) <= period;
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when "10" =>
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rdata(15 downto 0) <= hi_val;
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when "11" =>
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rdata(15 downto 0) <= lo_val;
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when others =>
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end case;
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rvalid <= '1';
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end if;
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if unsigned(wstrb) > 0 then
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case waddr(1 downto 0) is
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when "00" =>
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enabled <= wdata(0);
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when "01" =>
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period <= wdata(23 downto 8);
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when "10" =>
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hi_val <= wdata(15 downto 0);
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when "11" =>
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lo_val <= wdata(15 downto 0);
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when others =>
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end case;
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bvalid <= '1';
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onwrite <= '1';
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end if;
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end if;
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end process;
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end Behavioral;
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