342 lines
8.2 KiB
C
342 lines
8.2 KiB
C
/******************************************************************************
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* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xil_testcache.c
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* @addtogroup common_test_utils
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*
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a hbm 07/28/09 Initial release
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* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
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* cache line.
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* </pre>
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*
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******************************************************************************/
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#ifdef __ARM__
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#include "xil_cache.h"
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#include "xil_testcache.h"
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#include "xil_types.h"
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#include "xpseudo_asm.h"
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#ifdef __aarch64__
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#include "xreg_cortexa53.h"
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#else
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#include "xreg_cortexr5.h"
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#endif
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#include "xil_types.h"
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extern void xil_printf(const char8 *ctrl1, ...);
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#define DATA_LENGTH 128
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#ifdef __aarch64__
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static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
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#else
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static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
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#endif
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/*****************************************************************************/
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/**
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*
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* @brief Perform DCache range related API test such as Xil_DCacheFlushRange
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* and Xil_DCacheInvalidateRange. This test function writes a constant
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* value to the Data array, flushes the range, writes a new value, then
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* invalidates the corresponding range.
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*
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* @return
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* - -1 is returned for a failure
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* - 0 is returned for a pass
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*
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*****************************************************************************/
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s32 Xil_TestDCacheRange(void)
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{
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s32 Index;
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s32 Status = 0;
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u32 CtrlReg;
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INTPTR Value;
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xil_printf("-- Cache Range Test --\n\r");
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0xA0A00505;
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xil_printf(" initialize Data done:\r\n");
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Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
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xil_printf(" flush range done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0xA0A00505) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Flush worked\r\n");
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}
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else {
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xil_printf("Error: flush dcache range not working\r\n");
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}
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0xA0A0C505;
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Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = Index + 3;
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Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
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xil_printf(" invalidate dcache range done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0xA0A0A05;
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0xA0A0A05) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Invalidate worked\r\n");
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}
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else {
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xil_printf("Error: Invalidate dcache range not working\r\n");
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}
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xil_printf("-- Cache Range Test Complete --\r\n");
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return Status;
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}
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/*****************************************************************************/
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/**
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* @brief Perform DCache all related API test such as Xil_DCacheFlush and
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* Xil_DCacheInvalidate. This test function writes a constant value
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* to the Data array, flushes the DCache, writes a new value,
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* then invalidates the DCache.
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*
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* @return
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* - 0 is returned for a pass
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* - -1 is returned for a failure
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*****************************************************************************/
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s32 Xil_TestDCacheAll(void)
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{
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s32 Index;
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s32 Status;
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INTPTR Value;
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u32 CtrlReg;
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xil_printf("-- Cache All Test --\n\r");
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0x50500A0A;
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xil_printf(" initialize Data done:\r\n");
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Xil_DCacheFlush();
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xil_printf(" flush all done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0x50500A0A) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Flush all worked\r\n");
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}
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else {
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xil_printf("Error: Flush dcache all not working\r\n");
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}
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0x505FFA0A;
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Xil_DCacheFlush();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = Index + 3;
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Xil_DCacheInvalidate();
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xil_printf(" invalidate all done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0x50CFA0A;
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0x50CFA0A) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Invalidate all worked\r\n");
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}
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else {
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xil_printf("Error: Invalidate dcache all not working\r\n");
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}
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xil_printf("-- DCache all Test Complete --\n\r");
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return Status;
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}
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/*****************************************************************************/
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/**
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* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers.
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*
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* @return
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* - 0 is returned for a pass
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*
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* @note The function will hang if it fails.
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*****************************************************************************/
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s32 Xil_TestICacheRange(void)
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{
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Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
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Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
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Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
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xil_printf("-- Invalidate icache range done --\r\n");
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return 0;
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}
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/*****************************************************************************/
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/**
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* @brief Perform Xil_ICacheInvalidate() on a few function pointers.
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*
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* @return
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* - 0 is returned for a pass
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*
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* @note The function will hang if it fails.
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*****************************************************************************/
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s32 Xil_TestICacheAll(void)
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{
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Xil_ICacheInvalidate();
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xil_printf("-- Invalidate icache all done --\r\n");
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return 0;
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}
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#endif
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