library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity dsp is
port
(
clk: in std_logic;
rst: in std_logic;
led: out std_logic_vector(7 downto 0);
uart0_rx: in std_logic;
uart0_tx: out std_logic;
pdmout0_pin: out std_logic;
uart1_rx: in std_logic;
uart1_tx: out std_logic
);
end dsp;
architecture rtl of dsp is
component cpu is port
(
clk: in std_logic;
rst: in std_logic;
code_data: in std_logic_vector(15 downto 0);
code_addr: out std_logic_vector(15 downto 0);
mem_in: in std_logic_vector(15 downto 0);
mem_out: out std_logic_vector(15 downto 0);
mem_addr: out std_logic_vector(15 downto 0);
mem_write: out std_logic;
mem_read: out std_logic;
mem_busy: in std_logic
);
end component;
component ram is
generic
(
addressWidth : in positive := 16;
busWidth : in positive := 16;
size : in positive := 4096
);
port
(
clk : in std_logic;
-- port A
addra : in std_logic_vector(addressWidth - 1 downto 0);
wea : in std_logic;
dina : in std_logic_vector(busWidth - 1 downto 0);
douta : out std_logic_vector(busWidth - 1 downto 0);
-- port B (read only)
addrb : in std_logic_vector(addressWidth - 1 downto 0);
doutb : out std_logic_vector(busWidth - 1 downto 0)
);
end component;
component boot_rom is port
(
clk: in std_logic;
code_addr : in std_logic_vector(15 downto 0);
code_out : out std_logic_vector(15 downto 0);
data_addr : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0)
);
end component;
component uart is
generic
(
baudrate : in natural := 1_000_000
);
port
(
clk : in std_logic;
rst : in std_logic;
-- hardware
rx_pin : in std_logic;
tx_pin : out std_logic;
-- bus interface
we : in std_logic;
re : in std_logic;
addr : in std_logic_vector(15 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0)
);
end component;
component sysbus is
port
(
clk: in std_logic;
rst: in std_logic;
-- master port 0
m0_addr: in std_logic_vector(15 downto 0);
m0_wdata: in std_logic_vector(15 downto 0);
m0_rdata: out std_logic_vector(15 downto 0);
m0_re: in std_logic;
m0_we: in std_logic;
m0_busy: out std_logic;
-- master port 1
m1_addr: in std_logic_vector(15 downto 0);
m1_wdata: in std_logic_vector(15 downto 0);
m1_rdata: out std_logic_vector(15 downto 0);
m1_re: in std_logic;
m1_we: in std_logic;
m1_busy: out std_logic;
-- actual bus
bus_addr: out std_logic_vector(15 downto 0);
bus_wdata: out std_logic_vector(15 downto 0);
bus_rdata: in std_logic_vector(15 downto 0);
bus_re: out std_logic;
bus_we: out std_logic
);
end component;
component pdmout is
port
(
clk : in std_logic;
rst : in std_logic;
-- hardware
out_pin : out std_logic;
-- bus interface
we : in std_logic;
addr : in std_logic_vector(15 downto 0);
din : in std_logic_vector(15 downto 0)
);
end component;
component square is
port
(
clk : in std_logic;
rst : in std_logic;
-- bus slave interface
s_we : in std_logic;
s_addr : in std_logic_vector(15 downto 0);
s_din : in std_logic_vector(15 downto 0);
-- bus master interface (DMA!!)
m_busy : in std_logic;
m_we : out std_logic;
m_addr : out std_logic_vector(15 downto 0);
m_dout : out std_logic_vector(15 downto 0)
);
end component;
signal mem_wea : std_logic;
signal rom_code_addr, rom_code_out: std_logic_vector(15 downto 0);
signal mem_dina, mem_douta, mem_addra: std_logic_vector(15 downto 0);
signal mem_doutb, mem_addrb: std_logic_vector(15 downto 0);
signal rom_data_addr, rom_data_out: std_logic_vector(15 downto 0);
signal uart0_din, uart0_dout, uart0_addr: std_logic_vector(15 downto 0);
signal uart0_we, uart0_re: std_logic;
signal uart1_din, uart1_dout, uart1_addr: std_logic_vector(15 downto 0);
signal uart1_we, uart1_re: std_logic;
signal cpu_write, cpu_read, cpu_busy: std_logic;
signal cpu_mosi, cpu_miso, cpu_addr: std_logic_vector(15 downto 0);
signal square_write, square_busy: std_logic;
signal square_mosi, square_addr: std_logic_vector(15 downto 0);
signal square0_s_din, square0_s_addr: std_logic_vector(15 downto 0);
signal square0_s_we : std_logic;
signal pdmout0_din, pdmout0_addr: std_logic_vector(15 downto 0);
signal pdmout0_we : std_logic;
signal dbus_write, dbus_read: std_logic;
signal dbus_mosi, dbus_miso, dbus_addr: std_logic_vector(15 downto 0);
signal ibus_miso, ibus_addr: std_logic_vector(15 downto 0);
signal led_r, led_next: std_logic_vector(7 downto 0);
begin
cpu0: cpu port map(clk => clk, rst => rst,
code_data => ibus_miso, code_addr => ibus_addr,
mem_in => cpu_miso, mem_out => cpu_mosi, mem_addr => cpu_addr,
mem_write => cpu_write, mem_read => cpu_read, mem_busy => cpu_busy);
rom: boot_rom port map(clk => clk, code_addr => rom_code_addr, code_out => rom_code_out,
data_addr => rom_data_addr, data_out => rom_data_out);
mem: ram port map(clk => clk,
addra => mem_addra, wea => mem_wea, dina => mem_dina, douta => mem_douta,
addrb => mem_addrb, doutb => mem_doutb);
uart0: uart port map(clk => clk, rst => rst, rx_pin => uart0_rx, tx_pin => uart0_tx,
addr => uart0_addr, din => uart0_din, dout => uart0_dout,
re => uart0_re, we => uart0_we);
uart1: uart generic map(baudrate => 31250)
port map(clk => clk, rst => rst, rx_pin => uart1_rx, tx_pin => uart1_tx,
addr => uart1_addr, din => uart1_din, dout => uart1_dout,
re => uart1_re, we => uart1_we);
square0: square port map(clk => clk, rst => rst,
s_we => square0_s_we, s_addr => square0_s_addr, s_din => square0_s_din,
m_busy => square_busy, m_we => square_write,
m_addr => square_addr, m_dout => square_mosi);
pdmout0: pdmout port map(clk => clk, rst => rst,
out_pin => pdmout0_pin,
we => pdmout0_we, addr => pdmout0_addr, din => pdmout0_din);
main_bus: sysbus port map(clk => clk, rst => rst,
m0_addr => cpu_addr, m0_wdata => cpu_mosi, m0_rdata => cpu_miso,
m0_re => cpu_read, m0_we => cpu_write, m0_busy => cpu_busy,
m1_addr => square_addr, m1_wdata => square_mosi, m1_rdata => open,
m1_re => '0', m1_we => square_write, m1_busy => square_busy,
bus_addr => dbus_addr, bus_wdata => dbus_mosi, bus_rdata => dbus_miso,
bus_re => dbus_read, bus_we => dbus_write
);
-- system map
-- 0x0000 - 0x0fff ROM
-- 0x1000 - 0x1fff RAM
-- 0xc000 - 0xc00f LED0
-- 0xc010 - 0xc01f UART0 (1 Mbaud)
-- 0xc020 - 0xc02f PDMOUT0
-- 0xc030 - 0xc03f SQUARE0
-- 0xc040 - 0xc04f UART1 (31250 baud)
led <= led_r;
-- IBUS interconnect
mem_addrb <= x"0" & ibus_addr(11 downto 0);
rom_code_addr <= x"0" & ibus_addr(11 downto 0);
process(ibus_addr, rom_code_out, mem_doutb)
begin
case ibus_addr(15 downto 12) is
when x"0" =>
ibus_miso <= rom_code_out;
when x"1" =>
ibus_miso <= mem_doutb;
when others =>
ibus_miso <= x"0000";
end case;
end process;
-- LED
process(clk, rst)
begin
if rising_edge(clk) then
led_r <= led_next;
end if;
if rst = '1' then
led_r <= x"00";
end if;
end process;
-- DBUS interconnect
mem_addra <= x"0" & dbus_addr(11 downto 0);
rom_data_addr <= x"0" & dbus_addr(11 downto 0);
uart0_addr <= x"000" & dbus_addr(3 downto 0);
uart1_addr <= x"000" & dbus_addr(3 downto 0);
pdmout0_addr <= x"000" & dbus_addr(3 downto 0);
square0_s_addr <= x"000" & dbus_addr(3 downto 0);
process(dbus_addr, dbus_mosi, dbus_write, mem_douta, rst, rom_data_out, led_r, dbus_read, uart0_dout, uart1_dout)
begin
dbus_miso <= x"0000";
mem_dina <= dbus_mosi;
mem_wea <= '0';
led_next <= led_r;
uart0_din <= dbus_mosi;
uart0_we <= '0';
uart0_re <= '0';
uart1_din <= dbus_mosi;
uart1_we <= '0';
uart1_re <= '0';
pdmout0_we <= '0';
pdmout0_din <= dbus_mosi;
square0_s_we <= '0';
square0_s_din <= dbus_mosi;
case dbus_addr(15 downto 12) is
when x"0" =>
dbus_miso <= rom_data_out;
when x"1" =>
dbus_miso <= mem_douta;
mem_wea <= dbus_write;
when x"c" =>
case dbus_addr(7 downto 4) is
when x"0" => -- LED
if dbus_write = '1' then
led_next <= dbus_mosi(7 downto 0);
end if;
when x"1" => -- UART0
dbus_miso <= uart0_dout;
uart0_we <= dbus_write;
uart0_re <= dbus_read;
when x"2" => -- PDMOUT0
pdmout0_we <= dbus_write;
when x"3" => -- SQUARE0
square0_s_we <= dbus_write;
when x"4" => -- UART1
dbus_miso <= uart1_dout;
uart1_we <= dbus_write;
uart1_re <= dbus_read;
when others =>
end case;
when others =>
end case;
end process;
end rtl;