library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

entity wave_test is
end wave_test;

architecture rtl of wave_test is

  component wave is
    port
    (
      -- AXI4 slave interface
      aclk    : in std_logic;
      aresetn : in std_logic;

      -- read addr
      araddr  : in std_logic_vector(31 downto 0);
      arvalid : in std_logic;
      arready : out std_logic;

      -- read data
      rdata   : out std_logic_vector(31 downto 0);
      rresp   : out std_logic;
      rvalid  : out std_logic;
      rready  : in std_logic;

      -- write addr
      awaddr  : in std_logic_vector(31 downto 0);
      awvalid : in std_logic;
      awready : out std_logic;

      -- write data
      wdata   : in std_logic_vector(31 downto 0);
      wstrb   : in std_logic_vector(3 downto 0);

      -- write resp
      bresp   : out std_logic;
      bvalid  : out std_logic;
      bready  : in std_logic;


      -- PDM output!
      pdmout  : out std_logic
    );
  end component;

  signal finished, clk, rst, rstn: std_logic := '0';

  signal arvalid, arready, awvalid, awready: std_logic;
  signal rresp, rvalid, rready, bresp, bvalid, bready: std_logic;
  signal wstrb: std_logic_vector(3 downto 0);
  signal araddr, rdata, awaddr, wdata: std_logic_vector(31 downto 0);

  signal pdmout: std_logic;

  constant period: integer := 7 * 256;
  constant half_time: time := 1280 ns * period;

begin
  rstn <= not rst;
  dut: wave port map(aclk => clk, aresetn => rstn,
  arvalid => arvalid, arready => arready, awvalid => awvalid, awready => awready,
  rresp => rresp, rvalid => rvalid, rready => rready, bresp => bresp, bvalid => bvalid, bready => bready,
  wstrb => wstrb, araddr => araddr, rdata => rdata, awaddr => awaddr, wdata => wdata,
  pdmout => pdmout
                    );

  -- tick tock
  process
  begin
    if finished = '0' then
      clk <= not clk;
      wait for 5 ns;
    else
      clk <= '0';
      wait;
    end if;
  end process;

  process
  begin
    rst <= '1';

    arvalid <= '0';
    awvalid <= '0';
    wstrb <= "0000";

    wait for 1 ns;
--    assert(='0') report "Fail rst" severity error;

    rst <= '0';

    wait for 10 ns;

    awvalid <= '1';
    awaddr <= x"00000000";  -- enable
    wstrb <= "1111";
    wdata <= x"00000001";
    bready <= '1';

    wait for 10 ns;
    assert(bvalid = '1') report "Write error" severity error;
    assert(bresp = '0') report "Write fail" severity error;
    assert(awready = '1') report "Write error" severity error;

    awaddr <= x"00000004";  -- period
    wdata <= std_logic_vector(to_unsigned(period, 32));

    wait for 10 ns;

    -- read back
    wstrb <= "0000";
    awvalid <= '0';
    arvalid <= '1';
    araddr <= x"00000004";
    rready <= '1';

    wait for 10 ns;
    assert(unsigned(rdata) = period) report "Period readback failed" severity error;

    arvalid <= '0';
    awvalid <= '1';
    wstrb <= "1111";

    awaddr <= x"00000008"; -- high
    wdata <= x"00008000";

    wait for 10 ns;

    awaddr <= x"0000000c"; -- low
    wdata <= x"00004000";

    wait for 10 ns;

    wstrb <= "0000";
    awvalid <= '0';

    wait for 30 ns;
    assert(pdmout = '1') report "wrong pdmout" severity error;
    wait for 10 ns;
    assert(pdmout = '0') report "wrong pdmout" severity error;
    wait for 10 ns;
    assert(pdmout = '0') report "wrong pdmout" severity error;
    wait for 10 ns;
    assert(pdmout = '1') report "wrong pdmout" severity error;
    wait for 10 ns;
    assert(pdmout = '0') report "wrong pdmout" severity error;
    wait for 10 ns;
    assert(pdmout = '0') report "wrong pdmout" severity error;
    wait for 10 ns;
    assert(pdmout = '0') report "wrong pdmout" severity error;
    wait for 10 ns;
    assert(pdmout = '1') report "wrong pdmout" severity error;

    wait for 100 us;

    assert false report "Test done." severity note;

    finished <= '1';
    wait;

  end process;
end rtl;