library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

entity rom_test is
  end rom_test;

architecture rtl of rom_test is

  component clock is
    port(clk: out std_logic);
  end component;

  component dff is
    port(
          clk: in std_logic;
          rst: in std_logic;

          d: in std_logic;
          q: out std_logic
        );
  end component;

  component rom is port (
                          address : in unsigned(15 downto 0);
                          dataOut : out std_logic_vector(15 downto 0)
                        );
  end component;

  signal clk, rst: std_logic;
  signal romout, regq: std_logic_vector(15 downto 0);
  signal addr: unsigned(15 downto 0);

begin
  heartbeat: clock port map(clk);
  dut: rom port map(addr, romout);

  reg:
  for i in 15 downto 0 generate
    regx: dff port map(clk, rst, romout(i), regq(i));
  end generate reg;

  process(regq) begin
    addr <=unsigned(regq);
  end process;

  process
  begin
    rst <= '1';

    wait for 1 ns;
    assert(regq(0)='0') report "Fail rst" severity error;

    rst <= '0';

    wait for 10 ns;
    assert(to_integer(unsigned(regq))=2) report "Fail rom read @0" severity error;

    wait for 10 ns;
    assert(to_integer(unsigned(regq))=4) report "Fail rom read @2" severity error;

    assert false report "Test done." severity note;
    wait;
  end process;
end rtl;