-- Simple OR gate design
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;

entity dff_test is
  end dff_test;

architecture rtl of dff_test is

  component clock is
    port(clk: out std_logic);
  end component;

  component dff is
    port(
          clk: in std_logic;
          rst: in std_logic;

          d: in std_logic;
          q: out std_logic
        );
  end component;

  signal d, q, clk, rst: std_logic;

begin
  heartbeat: clock port map(clk);
  dut: dff port map(clk, rst, d, q);

  process
  begin
    rst <= '1';

    wait for 10 ns;
    assert(q='0') report "Fail rst" severity error;

    rst <= '0';
    d <= '1';
    wait for 10 ns;
    assert(q='1') report "Fail d=1" severity error;

    rst <= '1';
    wait for 1 ns;
    assert(q='0') report "Async rst fail" severity error;
    rst <= '0';
    d <= '1';
    wait for 9 ns;

    d <= '0';
    wait for 1 ns;
    assert(q='1') report "Fail clk sync" severity error;
    wait for 9 ns;
    assert(q='0') report "Fail d=0" severity error;

    assert false report "Test done." severity note;
    wait;
  end process;
end rtl;