library IEEE;
use IEEE.std_logic_1164.all;

entity dff is
  port(
  clk : in std_logic;
  rst : in std_logic;

  d : in std_logic;
  q : out std_logic
);
end entity dff;

architecture behavior of dff is
begin
  process(clk, rst) is
  begin
    if (rst = '1') then
      q <= '0';
    else
      if rising_edge(clk) then
        q <= d;
      end if;
    end if;
  end process;
end architecture behavior;