library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity boot_rom is
  generic
  (
    addressWidth : in positive := 16;
    busWidth : in positive := 16
  );
  port
  (
    clk: in std_logic;
    code_addr : in std_logic_vector(15 downto 0);
    code_out : out std_logic_vector(15 downto 0);

    data_addr : in std_logic_vector(15 downto 0);
    data_out : out std_logic_vector(15 downto 0)
  );
end boot_rom;

architecture Behavioral of boot_rom is
  constant alignment: positive := busWidth / 8;
  constant romsize: natural := $nwords;

  type romtype is array(0 to romsize - 1) of std_logic_vector(15 downto 0);
  signal romdata: romtype := (
$words
  );
begin

  process(clk) is
    variable code_index: natural;
    variable data_index: natural;
  begin
    if rising_edge(clk) then
    code_index := to_integer(unsigned(code_addr)) / alignment;
    if code_index < romsize then
      code_out <= romdata(code_index);
    else
      code_out <= x"0000";
    end if;

    data_index := to_integer(unsigned(data_addr)) / alignment;
     data_out <= romdata(data_index);
     end if;
  end process;

end Behavioral;