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13 Commits

Author SHA1 Message Date
55c6be3d00 wave: axi4-compliant wave 2025-10-30 07:54:33 -04:00
23a4a69670 wave: Makefile 2025-10-30 07:51:53 -04:00
b8d828c438 cc: make it work with modern lark 2025-09-12 12:35:06 +02:00
467ef32107 mbv: add make precommit 2025-09-04 15:04:56 +02:00
9edebe637b mbv: move a few things around 2025-09-04 15:01:50 +02:00
dd51b5d610 mbv: async debugging in progres... 2025-07-21 10:07:21 +02:00
f0f26af791 mbv: i really though async would work this time
There's still a glitch/race somewhere.
2025-06-29 13:56:58 -07:00
724f8db1b1 mbv: fix async uart2 app. it works! 2025-06-28 18:21:11 -07:00
269a04d5f5 mbv: fix bug in xuartlite 2025-06-27 13:01:20 -07:00
2e640690ba mbv: global constructors ish 2025-06-27 13:01:06 -07:00
e7b38fb560 mbv: debugging the async app 2025-06-27 13:00:29 -07:00
e4936abb53 mbv: black 2025-06-25 08:39:33 -07:00
7f1f924331 mbv: clang-format 2025-06-25 08:38:46 -07:00
76 changed files with 807 additions and 531 deletions

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@@ -26,16 +26,20 @@ dev-image:
dev: dev-image ## Run a dev container
docker run -it --rm -v $(CURDIR):/workspace -w /workspace mbv-dev
.PHONY: precommit
precommit: ## Make sure everything looks ok before pushing
$(MAKE) bootloader
$(MAKE) helloworld
$(MAKE) timer
$(MAKE) uart
$(MAKE) async
.PHONY: clean
clean: ## Remove generated files
rm -rf *.elf *.bin $(all_objects) $(deps)
rm -rf test/ *.dSYM $(test_deps) *.o
rm -rf *.elf *.bin
.PHONY: help
help: ## Show this help
@echo Noteworthy targets:
@egrep '^[a-zA-Z_-]+:.*?## .*$$' $(firstword $(MAKEFILE_LIST)) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-20s\033[0m %s\n", $$1, $$2}'
.DEFAULT_GOAL := help
#-include $(deps)
#-include $(test_deps)

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@@ -21,6 +21,13 @@ SECTIONS
*(.rodata*)
} > RAM
.init :
{
__init_array_start = .;
KEEP(*(.init_array*))
__init_array_end = .;
}
.bss (NOLOAD) :
{
_bss_begin = .;

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@@ -1,27 +0,0 @@
#pragma once
#include <cstdint>
struct Gpio {
volatile uint32_t data;
};
#define gpio0 ((Gpio*)0x40000000)
inline void ToggleLed(int which) {
uint8_t data = gpio0->data;
data ^= (0x1 << which);
gpio0->data = data;
}
inline void SetLed(int which) {
uint8_t data = gpio0->data;
data |= (0x1 << which);
gpio0->data = data;
}
inline void ClearLed(int which) {
uint8_t data = gpio0->data;
data &= ~(0x1 << which);
gpio0->data = data;
}

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@@ -1,26 +1,58 @@
#include "async.h"
#include "buffer.h"
#include "gpio.h"
#include "intc.h"
#include "interrupts.h"
#include "pol0.h"
#include "timer.h"
#include "trace.h"
#include "hal/gpio.h"
#include "hal/intc.h"
#include "hal/interrupts.h"
#include "hal/pol0.h"
#include "hal/timer.h"
#include "lib/async.h"
#include "lib/buffer.h"
#include "uart.h"
#include "uart_async.h"
namespace {
using async::AwaitableType;
Timer* timer0;
constexpr uint32_t kTicksPerSecond = 100'000'000;
constexpr uint32_t kTicksPerMicrosecond = 100;
constexpr uint32_t kOverflowSeconds = (1ULL << 32) / kTicksPerSecond;
constexpr uint32_t kOverflowMicroseconds =
((1ULL << 32) % kTicksPerSecond) / kTicksPerMicrosecond;
void Uart0Isr() {
ToggleLed(7);
HandleUartIsr();
Timer* timer0;
volatile uint32_t t1overflowsecs = 0;
volatile uint32_t t1overflowusecs = 0;
Gpio* gpio0;
void ToggleLed(int which) {
uint8_t data = gpio0->data;
data ^= (0x1 << which);
gpio0->data = data;
}
void SetLed(int which) {
uint8_t data = gpio0->data;
data |= (0x1 << which);
gpio0->data = data;
}
void ClearLed(int which) {
uint8_t data = gpio0->data;
data &= ~(0x1 << which);
gpio0->data = data;
}
void Uart0Isr() { HandleUartIsr(); }
void Timer0Isr() {
if (timer0->HasT1Overflowed()) {
UartWriteCrash("t1 overflow\r\n");
t1overflowsecs += kOverflowSeconds;
t1overflowusecs += kOverflowMicroseconds;
timer0->ClearT1Overflow();
return;
}
SetLed(6);
UartWriteCrash("blarg\r\n");
__builtin_trap();
}
@@ -48,43 +80,49 @@ void SetupInterrupts() {
}
async::task<> echo() {
async::task<uint8_t> reader = UartReadLoop();
async::task<std::byte> reader = UartReadLoop();
async::gimme<std::span<const std::byte>> feeder;
async::task<> writer = UartWriteLoop(feeder);
writer.h.resume(); // advance to first yield
while (1) {
SetLed(1);
uint8_t c = co_await reader;
std::byte c = co_await reader;
ClearLed(1);
ToggleLed(2);
feeder.feed(std::as_bytes(std::span{&c, 1}));
co_await feeder.feed(std::span{&c, 1});
}
}
async::task<> blink() {
while (1) {
co_await async::delay(500);
ToggleLed(0);
timer0->Pet();
co_await UartWrite(".");
}
}
} // namespace
#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
int main() {
SetupUart();
UartWriteCrash("uart setup done\r\n");
SetupTimer();
UartWriteCrash("timer setup done\r\n");
gpio0 = Gpio::Instance(GPIO0_BASE);
gpio0->data = 0;
SetupUart();
UartWriteBlocking("uart setup done\r\n");
SetupTimer();
UartWriteBlocking("timer setup done\r\n");
SetupInterrupts();
async::schedule(echo().h);
auto e = echo();
auto b = blink();
async::schedule(e.h);
async::schedule(b.h);
UartWriteCrash("init done. starting main loop\r\n");
UartWriteBlocking("init done. starting main loop\r\n");
async::main_loop([]() {
static int cnt = 0;
timer0->Pet();
if ((cnt++ % 100000) == 0) {
ToggleLed(0);
}
return false;
});
// should never get here
@@ -96,12 +134,7 @@ int main() {
#include <cstdint>
#include "itoa.h"
#include "lock.h"
#ifndef SBRK_STATS
#define SBRK_STATS 0
#endif
#include "lib/lock.h"
extern unsigned char _heap_begin, _heap_end;
@@ -119,8 +152,9 @@ extern "C" void* _sbrk(int increment) {
extern "C" int _gettimeofday(struct timeval* tv, void* tzvp) {
(void)tzvp;
uint32_t ticks = timer0->GetT1Ticks();
tv->tv_sec = ticks / 100000000;
tv->tv_usec = (ticks % 100000000) / 100;
tv->tv_sec = ticks / kTicksPerSecond + t1overflowsecs;
tv->tv_usec =
(ticks % kTicksPerSecond) / kTicksPerMicrosecond + t1overflowusecs;
return 0;
}

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@@ -1,71 +0,0 @@
#include "trace.h"
#include <algorithm>
#include <chrono>
#include "itoa.h"
#include "lock.h"
#include "uart.h"
namespace tracing {
namespace {
struct Event {
uint32_t timestamp;
TraceEvent event;
};
constexpr size_t kTraceBufferSize = 256;
std::array<Event, kTraceBufferSize> buffer;
size_t write_ptr = 0;
size_t size = 0;
} // namespace
void trace(int raw_event) { trace(static_cast<TraceEvent>(raw_event)); }
void trace(TraceEvent event) {
const std::chrono::system_clock::time_point now =
std::chrono::system_clock::now();
const uint32_t uptime_ticks = now.time_since_epoch().count();
{
InterruptLock lock;
buffer[write_ptr] = {.timestamp = uptime_ticks, .event = event};
write_ptr = (write_ptr + 1) % buffer.size();
size = std::min(size + 1, kTraceBufferSize);
#if TRACE_DUMP_WHEN_FULL
if (size == kTraceBufferSize) {
dump();
}
#endif // TRACE_DUMP_WHEN_FULL
}
}
void dump() {
InterruptLock lock;
if (size == kTraceBufferSize) {
std::rotate(buffer.begin(), buffer.begin() + write_ptr, buffer.end());
}
char number[] = "00000000";
UartWriteCrash("----\r\n");
for (Event event : std::span{buffer}.subspan(0, size)) {
itoa(static_cast<int>(event.timestamp), number);
UartWriteCrash(number);
UartWriteCrash(" ");
itoa(static_cast<int>(event.event), number);
UartWriteCrash(number);
UartWriteCrash("\r\n");
}
UartWriteCrash("----\r\n");
size = 0;
write_ptr = 0;
}
} // namespace tracing

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@@ -1,51 +0,0 @@
#pragma once
#define TRACE_DUMP_WHEN_FULL 0
#ifdef __x86_64__
#include <cstdio>
#define TRACE(x) printf(#x "\n")
#else // __x86_64__
#define TRACE(...) tracing::trace(__VA_ARGS__)
#endif // __x86_64__
#include <cstdint>
namespace tracing {
enum class TraceEvent : uint8_t {
kUnknown = 0,
kUartIsr = 1,
kUartRxCb = 2,
kUartTxCb = 3,
kUartSend = 10,
kUartRecv = 11,
kUartTxBufferFull = 12,
kUartTxBufferNotFull = 13,
kUartWriteDone = 20,
kAsyncResume = 4,
kAsyncEnqueue = 5,
kAsyncTask = 6,
kAsyncResumeSetPending = 7,
kAsyncAwaitWasNotified = 8,
kAsyncSchedule = 9,
kAsyncTaskDone = 14,
kAsyncException = 15,
kAsyncCallParent = 16,
kAsyncCallParentDone = 17,
kAsyncCoAwait = 18,
kAsyncSuspend = 19,
kAsyncDestroy = 21,
kAsyncGimmeWaiting = 22,
kAsyncGimmeResume = 23,
};
void trace(TraceEvent event);
void trace(int raw_event);
void dump();
} // namespace tracing

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@@ -1,14 +1,14 @@
#include "uart.h"
#include "async.h"
#include "gpio.h"
#include "lock.h"
#include "pol0.h"
#include "ring_buffer.h"
#include "trace.h"
#include "uart_async.h"
#include "hal/gpio.h"
#include "hal/pol0.h"
#include "lib/async.h"
#include "lib/lock.h"
#include "lib/ring_buffer.h"
#include "xuartlite.h"
#include "uart_async.h"
namespace {
using async::AwaitableType;
@@ -22,11 +22,43 @@ XUartLite_Config uart0_config = {
.DataBits = 8,
};
constexpr size_t kUartRxBufferSize = 256;
std::array<std::byte, kUartRxBufferSize> rx_buffer = {};
RingBuffer rx_ring_buffer{.buffer = rx_buffer};
constexpr size_t kUartTxBufferSize = 256;
std::array<std::byte, kUartTxBufferSize> tx_buffer = {};
RingBuffer tx_ring_buffer{.buffer = tx_buffer};
XUartLite* uart0 = &uart0_inst;
volatile bool sending;
void StartReceiving() {
while (1) {
if (rx_ring_buffer.FreeSpace() < 1) {
// woops, full. discard some data
// TODO: keep track of overrun stats
rx_ring_buffer.Pop(1);
}
if (XUartLite_Recv(uart0, rx_ring_buffer.RawWritePointer(), 1) < 1) {
break;
}
rx_ring_buffer.Push(1);
}
}
void StartSending() {
if (sending) {
return;
}
size_t tosend = tx_ring_buffer.ContiguousAvailableData();
if (tosend < 1) {
return;
}
sending = true;
XUartLite_Send(uart0, tx_ring_buffer.RawReadPointer(), tosend);
}
} // namespace
void InitUarts() {
@@ -34,10 +66,14 @@ void InitUarts() {
XUartLite_SetSendHandler(uart0, HandleUartTxFromIsr, nullptr);
XUartLite_SetRecvHandler(uart0, HandleUartRxFromIsr, nullptr);
StartReceiving();
XUartLite_EnableInterrupt(uart0);
sending = false;
}
void UartWriteCrash(std::span<const std::byte> data) {
XUartLite_DisableInterrupt(uart0);
while (data.size() > 0) {
while (XUartLite_IsSending(uart0)) {
}
@@ -48,22 +84,19 @@ void UartWriteCrash(std::span<const std::byte> data) {
}
while (XUartLite_IsSending(uart0)) {
}
XUartLite_Send(uart0, nullptr,
0); // reset buffer before enabling interrupts
XUartLite_EnableInterrupt(uart0);
}
async::task<> UartWrite(std::span<const std::byte> data) {
while (!tx_ring_buffer.Store(data)) {
tracing::trace(tracing::TraceEvent::kUartTxBufferFull);
co_await async::await(AwaitableType::kUartTx);
tracing::trace(tracing::TraceEvent::kUartTxBufferNotFull);
}
{
InterruptLock lock;
if (!XUartLite_IsSending(uart0)) {
tracing::trace(tracing::TraceEvent::kUartSend);
XUartLite_Send(uart0, tx_ring_buffer.RawReadPointer(),
tx_ring_buffer.ContiguousAvailableData());
}
StartSending();
}
}
@@ -72,29 +105,19 @@ async::task<> UartWriteLoop(
while (1) {
auto data = co_await data_gen;
while (!tx_ring_buffer.Store(data)) {
tracing::trace(tracing::TraceEvent::kUartTxBufferFull);
co_await async::await(AwaitableType::kUartTx);
tracing::trace(tracing::TraceEvent::kUartTxBufferNotFull);
}
{
InterruptLock lock;
if (!XUartLite_IsSending(uart0)) {
tracing::trace(tracing::TraceEvent::kUartSend);
XUartLite_Send(uart0, tx_ring_buffer.RawReadPointer(),
tx_ring_buffer.ContiguousAvailableData());
}
StartSending();
}
}
}
// TODO: use chunks to allow receiving more than 256 bytes at once
void UartReadBlocking(std::span<std::byte> data) {
size_t bytes_received = 0;
while (bytes_received < data.size()) {
auto* buffer = reinterpret_cast<uint8_t*>(data.data() + bytes_received);
tracing::trace(tracing::TraceEvent::kUartRecv);
bytes_received +=
XUartLite_Recv(uart0, buffer, data.size() - bytes_received);
while (!rx_ring_buffer.Load(data)) {
}
}
@@ -104,21 +127,14 @@ void UartWriteBlocking(std::span<const std::byte> data) {
{
InterruptLock lock;
if (!XUartLite_IsSending(uart0)) {
tracing::trace(tracing::TraceEvent::kUartSend);
XUartLite_Send(uart0, tx_ring_buffer.RawReadPointer(),
tx_ring_buffer.ContiguousAvailableData());
}
StartSending();
}
}
async::task<uint8_t> UartReadLoop() {
uint8_t c;
async::task<std::byte> UartReadLoop() {
std::byte c;
while (1) {
tracing::trace(tracing::TraceEvent::kUartRecv);
size_t received = XUartLite_Recv(uart0, &c, 1);
// some data may already be in the fifo, but if not, wait:
if (received < 1) {
while (!rx_ring_buffer.Load(std::span{&c, 1})) {
co_await async::await(AwaitableType::kUartRx);
}
@@ -128,38 +144,23 @@ async::task<uint8_t> UartReadLoop() {
async::task<buffer> UartRead(int size) {
auto buff = buffer::make(size);
auto* data = reinterpret_cast<uint8_t*>(buff.data.data());
tracing::trace(tracing::TraceEvent::kUartRecv);
size_t received = XUartLite_Recv(uart0, data, buff.data.size());
// some data may already be in the fifo, but if not, wait:
if (received < buff.data.size()) {
while (!rx_ring_buffer.Load(buff.data)) {
co_await async::await(AwaitableType::kUartRx);
}
co_return buff;
}
void HandleUartTxFromIsr(void*, unsigned int transmitted) {
sending = false;
tx_ring_buffer.Pop(transmitted);
if (tx_ring_buffer.AvailableData() > 0) {
tracing::trace(tracing::TraceEvent::kUartSend);
XUartLite_Send(uart0, tx_ring_buffer.RawReadPointer(),
tx_ring_buffer.ContiguousAvailableData());
}
StartSending();
async::resume(AwaitableType::kUartTx);
}
void HandleUartRxFromIsr(void*, unsigned int) {
void HandleUartRxFromIsr(void*, unsigned int transmitted) {
rx_ring_buffer.Push(transmitted);
StartReceiving();
async::resume(AwaitableType::kUartRx);
}
void HandleUartIsr() { XUartLite_InterruptHandler(uart0); }
extern "C" uint8_t XUartLite_GetSR(XUartLite*);
uint8_t UartStatus() { return XUartLite_GetSR(uart0); }
void LogStuff() {
uint8_t data = gpio0->data;
data |= (uart0->ReceiveBuffer.RemainingBytes & 0xf) << 4;
gpio0->data = data;
}

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@@ -3,11 +3,11 @@
#include <span>
#include <string_view>
#include "async.h"
#include "buffer.h"
#include "lib/async.h"
#include "lib/buffer.h"
async::task<buffer> UartRead(int size);
async::task<uint8_t> UartReadLoop();
async::task<std::byte> UartReadLoop();
async::task<> UartWrite(std::span<const std::byte> data);
inline async::task<> UartWrite(std::string_view s) {
co_await UartWrite(std::as_bytes(std::span{s.data(), s.size()}));

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@@ -1,7 +1,7 @@
#include <cstdint>
#include "gpio.h"
#include "pol0.h"
#include "hal/gpio.h"
#include "hal/pol0.h"
namespace {
@@ -10,7 +10,7 @@ Gpio* gpio0;
void sleep(int ms) {
for (int m = 0; m < ms; m++) {
for (int i = 0; i < 10000; i++) {
asm volatile ( "" );
asm volatile("");
}
}
}

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@@ -1,11 +1,12 @@
#include <cstdint>
#include "bios.h"
#include "gpio.h"
#include "intc.h"
#include "interrupts.h"
#include "pol0.h"
#include "timer.h"
#include "hal/bios.h"
#include "hal/gpio.h"
#include "hal/intc.h"
#include "hal/interrupts.h"
#include "hal/pol0.h"
#include "hal/timer.h"
namespace {

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@@ -1,9 +1,9 @@
#include <cstdint>
#include "gpio.h"
#include "intc.h"
#include "interrupts.h"
#include "pol0.h"
#include "hal/gpio.h"
#include "hal/intc.h"
#include "hal/interrupts.h"
#include "hal/pol0.h"
#include "xuartlite.h"
namespace {
@@ -23,16 +23,11 @@ XUartLite* uart0 = &uart0_inst;
volatile int incoming = 0;
void HandleUartRxFromIsr(void*, unsigned int) {
incoming += 1;
}
void HandleUartRxFromIsr(void*, unsigned int) { incoming += 1; }
void HandleUartTxFromIsr(void*, unsigned int) {
}
void HandleUartTxFromIsr(void*, unsigned int) {}
void Uart0Isr() {
XUartLite_InterruptHandler(uart0);
}
void Uart0Isr() { XUartLite_InterruptHandler(uart0); }
void InitUarts() {
XUartLite_CfgInitialize(uart0, &uart0_config, uart0_config.RegBaseAddr);
@@ -62,7 +57,8 @@ int main() {
uint8_t c;
while (XUartLite_Recv(uart0, &c, 1) > 0) {
XUartLite_Send(uart0, &c, 1);
while (XUartLite_IsSending(uart0)) {}
while (XUartLite_IsSending(uart0)) {
}
}
leds->data = 0xa1;
while (1) {
@@ -71,10 +67,12 @@ int main() {
counter += 1;
leds->data = counter;
XUartLite_Send(uart0, &c, 1);
while (XUartLite_IsSending(uart0)) {}
while (XUartLite_IsSending(uart0)) {
}
while (XUartLite_Recv(uart0, &c, 1) > 0) {
XUartLite_Send(uart0, &c, 1);
while (XUartLite_IsSending(uart0)) {}
while (XUartLite_IsSending(uart0)) {
}
}
incoming -= 1;
}

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@@ -1,6 +1,6 @@
#include <cstdint>
#include "pol0.h"
#include "hal/pol0.h"
#include "xuartlite.h"
uint8_t UartRead();
@@ -52,7 +52,8 @@ uint8_t UartRead() {
void UartWrite(uint8_t c) {
XUartLite_Send(uart0, &c, 1);
while (XUartLite_IsSending(uart0)) {}
while (XUartLite_IsSending(uart0)) {
}
}
int main() {

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@@ -88,8 +88,7 @@ int FindChar(const char* buf, uint8_t c) {
} // namespace
__attribute__((used))
void wozmon() {
__attribute__((used)) void wozmon() {
uint32_t cur_addr = 0;
uint32_t cur_data = 0;

19
mbv/configure vendored
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@@ -25,9 +25,9 @@ class Config:
hostlibs = "-lgtest -lgmock -lgtest_main"
hostldflags = "-fprofile-instr-generate -fcoverage-mapping"
include_dirs = [
"hal",
".",
"hal/uart",
"hal/lib/common",
"hal/xilinx",
]
common_flags = [
"-g",
@@ -269,10 +269,15 @@ hal = source_set("hal", [
"hal/intc.cc",
"hal/interrupts.cc",
"hal/start.cc",
"hal/lib/common/xil_assert.c",
"hal/uart/xuartlite.c",
"hal/uart/xuartlite_stats.c",
"hal/uart/xuartlite_intr.c",
"hal/uart/xuartlite_stats.c",
"hal/xilinx/xil_assert.c",
])
lib = source_set("lib", [
"lib/async.cc",
"lib/lock.cc",
])
bootloader = source_set("bootloader", glob.glob("./bootloader/**/*.cc", recursive=True))
@@ -289,23 +294,21 @@ def app_image(app, sources=None):
return build_image(
source_set(app, sources),
linker_script="apps/app.ld",
dependencies=[hal],
dependencies=[hal, lib],
elf_out=f"{app}.elf",
bin_out=f"{app}.bin",
)
all = [
build_source_set(hal),
build_source_set(lib),
bootloader_image,
app_image("helloworld"),
app_image("timer"),
app_image("uart"),
app_image("async", sources=[
"apps/async/async.cc",
"apps/async/lock.cc",
"apps/async/main.cc",
"apps/async/trace.cc",
"apps/async/uart.cc",
]),
]

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@@ -8,5 +8,4 @@ uint8_t BiosUartRead();
void BiosUartWrite(uint8_t);
void BiosWozmon();
void BiosUartWriteNibble(uint8_t);
}

View File

@@ -7,20 +7,17 @@ void BiosUartWrite(uint8_t);
void BiosWozmon();
void BiosUartWriteNibble(uint8_t n);
__attribute__((used))
void UartWriteU32(uint32_t a) {
__attribute__((used)) void UartWriteU32(uint32_t a) {
for (int i = 0; i < 8; i++) {
BiosUartWriteNibble(a >> 28);
a <<= 4;
}
}
__attribute__((used))
void UartWriteString(const char* s) {
__attribute__((used)) void UartWriteString(const char* s) {
while (*s) {
BiosUartWrite(*s);
s++;
}
}
}

View File

@@ -39,13 +39,9 @@ bool SetIrqEnabled(uint8_t irqn, bool enabled) {
return was_enabled;
}
void SetIsr(uint8_t irqn, Isr isr) {
isrs[irqn] = isr;
}
void SetIsr(uint8_t irqn, Isr isr) { isrs[irqn] = isr; }
void EnableInterrupts() {
intc->MER = 0x3;
}
void EnableInterrupts() { intc->MER = 0x3; }
void InterruptHandler() {
uint32_t ipr = intc->IPR;

View File

@@ -4,7 +4,7 @@
namespace intc {
using Isr = void(*)(void);
using Isr = void (*)(void);
/// Returns: true if the IRQ was previously enabled
bool SetIrqEnabled(uint8_t irqn, bool enabled);

View File

@@ -1,7 +1,8 @@
#include "interrupts.h"
#include <cstdint>
#include "bios.h"
#include "interrupts.h"
namespace {
@@ -12,8 +13,7 @@ constexpr uint32_t kInterruptCauseMask = 0xff;
Isr external_handler = nullptr;
__attribute__((interrupt))
void TrapHandler() {
__attribute__((interrupt)) void TrapHandler() {
uint32_t mcause;
uint32_t mip;
asm volatile("csrr %0, mcause" : "=r"(mcause));
@@ -26,7 +26,7 @@ void TrapHandler() {
}
mip &= ~(kMieExternalInterruptMask);
asm volatile("csrw mip, %0" :: "r"(mip));
asm volatile("csrw mip, %0" ::"r"(mip));
} else {
BiosWozmon();
}
@@ -34,18 +34,16 @@ void TrapHandler() {
} // namespace
void SetExternalInterruptHandler(Isr handler) {
external_handler = handler;
}
void SetExternalInterruptHandler(Isr handler) { external_handler = handler; }
void EnableExternalInterrupts() {
uint32_t mie;
Isr trap = TrapHandler;
asm volatile("csrr %0, mie" : "=r"(mie));
asm volatile("csrw mtvec, %0" :: "r"(trap));
asm volatile("csrw mtvec, %0" ::"r"(trap));
mie |= kMieExternalInterruptMask;
asm volatile("csrw mie, %0" :: "r"(mie));
asm volatile("csrw mie, %0" ::"r"(mie));
}
bool EnableInterrupts(bool on) {
@@ -61,6 +59,6 @@ bool EnableInterrupts(bool on) {
mstatus &= ~kMstatusMieMask;
}
asm volatile("csrw mstatus, %0" :: "r"(mstatus));
asm volatile("csrw mstatus, %0" ::"r"(mstatus));
return was_on;
}

View File

@@ -1,6 +1,6 @@
#pragma once
using Isr = void(*)();
using Isr = void (*)();
void SetExternalInterruptHandler(Isr handler);
void EnableExternalInterrupts();

View File

@@ -2,15 +2,17 @@
extern "C" uint32_t _bss_begin, _bss_end, _initial_stack_pointer;
extern "C" int main();
extern "C" void __libc_init_array();
__attribute__((section(".start"), used, naked))
void _start() {
__attribute__((section(".start"), used, naked)) void _start() {
// clear .bss
for (uint32_t* ptr = &_bss_begin; ptr < &_bss_end; ptr++) {
*ptr = 0;
}
asm volatile ( "la sp, _initial_stack_pointer" );
asm volatile("la sp, _initial_stack_pointer");
__libc_init_array();
main();

View File

@@ -37,11 +37,15 @@ struct Timer {
void EnableT1() {
TCSR1.ARHT0 = 1;
TCSR1.ENIT0 = 1; // enable interrupt for overflows
TCSR1.ENT0 = 1;
}
uint32_t GetT1Ticks() { return TCR1; }
bool HasT1Overflowed() { return TCSR1.T0INT; }
void ClearT1Overflow() { TCSR1.T0INT = 1; }
void SetupAsWdt(uint32_t timeout_ticks) {
TLR0 = timeout_ticks;
TCSR0.LOAD0 = 1; // reset counter
@@ -59,9 +63,7 @@ struct Timer {
TCSR0.ENT0 = 1;
}
void ClearInterrupt() {
TCSR0.T0INT = 0;
}
void ClearInterrupt() { TCSR0.T0INT = 0; }
static Timer* Instance(uint32_t base) {
return reinterpret_cast<Timer*>(base);

View File

@@ -1,39 +0,0 @@
DRIVER_LIB_VERSION = 1.0
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib/
INCLUDEDIR=../../../include/
INCLUDES=-I./. -I$(INCLUDEDIR)
SRCFILES:=$(wildcard *.c)
OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
libs: $(OBJECTS)
DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
include $(wildcard $(DEPFILES))
include $(wildcard ../../../../dep.mk)
$(RELEASEDIR)%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
.PHONY: include
include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
$(INCLUDEDIR)%.h: %.h
$(CP) $< $@
clean:
rm -rf ${OBJECTS}
rm -rf $(DEPFILES)

View File

@@ -387,8 +387,7 @@ int XUartLite_IsSending(XUartLite *InstancePtr)
/*
* Read the status register to determine if the transmitter is empty
*/
StatusRegister = XUartLite_ReadReg(InstancePtr->RegBaseAddress,
XUL_STATUS_REG_OFFSET);
StatusRegister = XUartLite_GetSR(InstancePtr);
/*
* If the transmitter is not empty then indicate that the UART is still

View File

@@ -143,8 +143,7 @@ void XUartLite_InterruptHandler(XUartLite *InstancePtr)
* Read the status register to determine which, coulb be both
* interrupt is active
*/
IsrStatus = XUartLite_ReadReg(InstancePtr->RegBaseAddress,
XUL_STATUS_REG_OFFSET);
IsrStatus = XUartLite_GetSR(InstancePtr);
if ((IsrStatus & (XUL_SR_RX_FIFO_FULL |
XUL_SR_RX_FIFO_VALID_DATA)) != 0) {

View File

@@ -6,7 +6,6 @@
#include <utility>
#include "lock.h"
#include "trace.h"
namespace async {
namespace {
@@ -33,7 +32,6 @@ std::array<Notification, static_cast<size_t>(AwaitableType::kNumTypes)>
void schedule(std::coroutine_handle<> h, int ms) {
InterruptLock lock;
TRACE(tracing::TraceEvent::kAsyncSchedule);
std::chrono::system_clock::time_point exp =
std::chrono::system_clock::now() + std::chrono::milliseconds(ms);
Stuff* news = new Stuff{
@@ -80,13 +78,7 @@ void step() {
int stuffinqueue = 0;
for (Stuff* s = stuff; s; s = s->next) stuffinqueue++;
TRACE(tracing::TraceEvent::kAsyncTask);
stuff->h();
TRACE(tracing::TraceEvent::kAsyncTaskDone);
if (stuff->h.done()) {
stuff->h.destroy();
}
{
InterruptLock lock;
@@ -124,12 +116,10 @@ void enqueue(std::coroutine_handle<> h, AwaitableType type) {
{
InterruptLock lock;
TRACE(tracing::TraceEvent::kAsyncEnqueue);
const bool was_notified =
std::exchange(notifications[ttype].pending, false);
if (was_notified) {
TRACE(tracing::TraceEvent::kAsyncAwaitWasNotified);
schedule(h);
return;
}

View File

@@ -4,61 +4,17 @@
#include <coroutine>
#include <utility>
#include "trace.h"
namespace async {
struct task_final_suspend {
bool await_ready() noexcept(true) { return false; }
void await_suspend(std::coroutine_handle<> h) noexcept(true) {
struct continuation : std::suspend_always {
void await_suspend(std::coroutine_handle<>) noexcept {
if (parent) {
TRACE(tracing::TraceEvent::kAsyncCallParent);
parent();
TRACE(tracing::TraceEvent::kAsyncCallParentDone);
if (parent && parent.done()) {
TRACE(tracing::TraceEvent::kAsyncDestroy);
parent.destroy();
parent.resume();
}
}
}
void await_resume() noexcept(true) {}
std::coroutine_handle<> parent;
};
template <typename T>
struct gimme {
// child interface
bool await_ready() { return false; }
void await_suspend(std::coroutine_handle<> h) {
ha = h;
waiting = true;
TRACE(tracing::TraceEvent::kAsyncGimmeWaiting);
}
T await_resume() {
waiting = false;
TRACE(tracing::TraceEvent::kAsyncGimmeResume);
return std::move(stuff);
}
// parent interface
void feed(T&& s) {
if (!waiting) {
__builtin_trap();
}
if (!ha) {
__builtin_trap();
}
stuff = s;
ha.resume();
}
bool waiting = false;
std::coroutine_handle<> ha;
T stuff;
};
template <typename T = void>
struct task;
@@ -67,40 +23,37 @@ struct task<void> {
struct promise_type;
using handle_type = std::coroutine_handle<promise_type>;
~task() {
if (h) {
h.destroy();
}
}
struct promise_type {
task get_return_object() {
return {.h = handle_type::from_promise(*this)};
}
std::suspend_always initial_suspend() noexcept { return {}; }
task_final_suspend final_suspend() noexcept {
return {.parent = parent};
}
continuation final_suspend() noexcept { return {.parent = parent}; }
void return_void() {}
void unhandled_exception() {
TRACE(tracing::TraceEvent::kAsyncException);
}
void unhandled_exception() {}
std::coroutine_handle<> parent;
};
// awaitable
bool await_ready() {
TRACE(tracing::TraceEvent::kAsyncCoAwait);
h();
h.promise().parent = {};
h.resume();
if (h.done()) {
TRACE(tracing::TraceEvent::kAsyncDestroy);
h.destroy();
return true;
}
return false;
}
void await_suspend(std::coroutine_handle<> ha) {
TRACE(tracing::TraceEvent::kAsyncSuspend);
h.promise().parent = ha;
}
void await_suspend(std::coroutine_handle<> ha) { h.promise().parent = ha; }
void await_resume() {}
std::coroutine_handle<promise_type> h;
handle_type h;
};
template <typename T>
@@ -108,20 +61,22 @@ struct task {
struct promise_type;
using handle_type = std::coroutine_handle<promise_type>;
~task() {
if (h) {
h.destroy();
}
}
struct promise_type {
task get_return_object() {
return {.h = handle_type::from_promise(*this)};
}
std::suspend_always initial_suspend() noexcept { return {}; }
task_final_suspend final_suspend() noexcept {
return {.parent = parent};
}
continuation final_suspend() noexcept { return {.parent = parent}; }
void return_value(T&& value) { ret_value = std::move(value); }
void unhandled_exception() {
TRACE(tracing::TraceEvent::kAsyncException);
}
void unhandled_exception() {}
template <std::convertible_to<T> From>
task_final_suspend yield_value(From&& value) {
continuation yield_value(From&& value) {
ret_value = std::forward<From>(value);
result_ready = true;
return {.parent = parent};
@@ -135,34 +90,18 @@ struct task {
// awaitable
bool await_ready() {
h.promise().parent = {};
TRACE(tracing::TraceEvent::kAsyncCoAwait);
h();
if (h.promise().result_ready) {
return true;
}
if (h.done()) {
destroyed = true;
ret_value = std::move(h.promise().ret_value);
TRACE(tracing::TraceEvent::kAsyncDestroy);
h.destroy();
h.resume();
if (h.promise().result_ready || h.done()) {
return true;
}
return false;
}
void await_suspend(std::coroutine_handle<> ha) {
TRACE(tracing::TraceEvent::kAsyncSuspend);
h.promise().parent = ha;
}
void await_suspend(std::coroutine_handle<> ha) { h.promise().parent = ha; }
T await_resume() {
if (!destroyed) {
h.promise().result_ready = false;
return std::move(h.promise().ret_value);
}
return std::move(ret_value);
}
bool destroyed = false;
T ret_value;
std::coroutine_handle<promise_type> h;
};
@@ -205,4 +144,50 @@ inline auto delay(int ms) {
return awaitable{ms};
}
template <typename T>
struct gimme {
// child interface
bool await_ready() { return false; }
void await_suspend(std::coroutine_handle<> h) {
ha = h;
waiting = true;
if (parent) {
schedule(parent);
}
}
T await_resume() {
waiting = false;
return std::move(stuff);
}
// parent interface
auto feed(T&& s) {
struct awaitable {
bool await_ready() {
g.parent = {};
g.ha.resume();
return g.waiting;
}
void await_suspend(std::coroutine_handle<> h) { g.parent = h; }
void await_resume() {}
gimme<T>& g;
};
if (!waiting) {
__builtin_trap();
}
if (!ha) {
__builtin_trap();
}
stuff = std::move(s);
return awaitable{.g = *this};
}
bool waiting = false;
std::coroutine_handle<> ha;
std::coroutine_handle<> parent;
T stuff;
};
} // namespace async

View File

@@ -1,7 +1,7 @@
#pragma once
#ifndef __x86_64__
#include "interrupts.h"
#include "hal/interrupts.h"
struct InterruptLock {
bool was_on;

View File

@@ -1,6 +1,5 @@
#pragma once
#include <atomic>
#include <span>
#include "lock.h"
@@ -8,9 +7,9 @@
struct RingBuffer {
std::span<std::byte> buffer;
std::atomic<size_t> read_ptr = 0;
std::atomic<size_t> write_ptr = 0;
std::atomic<bool> full = 0;
size_t read_ptr = 0;
size_t write_ptr = 0;
size_t used = 0;
bool Store(std::span<const std::byte> data) {
InterruptLock lock;
@@ -53,9 +52,7 @@ struct RingBuffer {
return false;
}
write_ptr = (write_ptr + amount) % buffer.size();
if (read_ptr == write_ptr) {
full = true;
}
used = used + amount;
return true;
}
@@ -66,25 +63,20 @@ struct RingBuffer {
return false;
}
read_ptr = (read_ptr + amount) % buffer.size();
if (amount > 0) {
full = false;
}
used = used - amount;
return true;
}
size_t FreeSpace() const {
InterruptLock lock;
return buffer.size() - AvailableData();
return buffer.size() - used;
}
size_t AvailableData() const {
InterruptLock lock;
if (read_ptr == write_ptr) {
return full ? buffer.size() : 0;
}
return (buffer.size() + write_ptr - read_ptr) % buffer.size();
return used;
}
uint8_t* RawReadPointer() const {
@@ -93,16 +85,21 @@ struct RingBuffer {
return reinterpret_cast<uint8_t*>(buffer.data() + read_ptr);
}
uint8_t* RawWritePointer() const {
InterruptLock lock;
return reinterpret_cast<uint8_t*>(buffer.data() + write_ptr);
}
size_t ContiguousFreeSpace() const {
InterruptLock lock;
return std::min(FreeSpace(), buffer.size() - write_ptr);
}
size_t ContiguousAvailableData() const {
InterruptLock lock;
if (read_ptr < write_ptr) {
return AvailableData();
}
if (full) {
return 0;
}
return buffer.size() - read_ptr;
return std::min(AvailableData(), buffer.size() - read_ptr);
}
};

View File

@@ -6,32 +6,32 @@ import threading
import time
offset = 0x80000000
tty = '/dev/ttyUSB1'
tty = "/dev/ttyUSB1"
baud = 115200
chunksize = 1024
def write(s, offset, dat):
for i in range(0, len(dat), chunksize):
chunk = dat[i: i + chunksize]
cmd = struct.pack('<cII', b'c', offset + i, len(chunk))
chunk = dat[i : i + chunksize]
cmd = struct.pack("<cII", b"c", offset + i, len(chunk))
print(f'Sending {len(chunk)} bytes @0x{offset + i:04x}')
print(f"Sending {len(chunk)} bytes @0x{offset + i:04x}")
s.write(cmd)
s.write(chunk)
ack = s.read(2)
if len(ack) < 2:
raise RuntimeError(f'timeout waiting for full ack. got {ack}')
if ack[0] != b'a'[0]:
raise RuntimeError(f'expected ack, got this instead: {ack}')
print(f'Ack! len={ack[1]}')
raise RuntimeError(f"timeout waiting for full ack. got {ack}")
if ack[0] != b"a"[0]:
raise RuntimeError(f"expected ack, got this instead: {ack}")
print(f"Ack! len={ack[1]}")
def jump(s, offset):
cmd = struct.pack('<cI', b'j', offset)
print(f'Jumping to 0x{offset:04x}')
cmd = struct.pack("<cI", b"j", offset)
print(f"Jumping to 0x{offset:04x}")
s.write(cmd)
@@ -40,21 +40,25 @@ def stream_logs(s):
dat = s.read()
if not dat:
continue
sys.stdout.buffer.write(dat.replace(b'\r', b''))
sys.stdout.buffer.write(dat.replace(b"\r", b""))
sys.stdout.buffer.flush()
def parse_args():
parser = argparse.ArgumentParser()
parser.add_argument("binary")
parser.add_argument("--monitor", action="store_true",
help="wait for and display program serial output")
parser.add_argument(
"--monitor",
action="store_true",
help="wait for and display program serial output",
)
return parser.parse_args()
def main():
args = parse_args()
with open(args.binary, 'rb') as f:
with open(args.binary, "rb") as f:
dat = f.read()
s = serial.Serial(tty, baud, timeout=1)
@@ -67,7 +71,7 @@ def main():
try:
while True:
dat = input("") + '\r'
dat = input("") + "\r"
s.write(dat.encode())
except KeyboardInterrupt:
print("Bye.")

62
mbv/testecho.py Normal file
View File

@@ -0,0 +1,62 @@
import argparse
import random
import serial
import sys
import threading
import time
tty = "/dev/ttyUSB1"
baud = 115200
def sendrecv(s, size, timeout=5):
"""Send some data and recv until the same data was received back."""
data = random.randbytes(size)
return sendcheck(s, data, timeout)
def sendcheck(s, data, timeout=5):
s.write(data)
received = 0
start = time.time()
got = bytearray()
while received < len(data):
r = s.read()
got += r
try:
assert(r == data[received: received + len(r)])
assert(time.time() < start + timeout)
except:
fr = received - 10
to = received + len(r) + 1
sdat = data[fr: to]
rdat = bytes(got[fr: to])
print(f"failed after receiving {received} correct bytes")
print(f"expected {sdat}")
print(f" got {rdat}")
sys.exit(-1)
received += len(r)
def parse_args():
parser = argparse.ArgumentParser()
return parser.parse_args()
def main():
args = parse_args()
s = serial.Serial(tty, baud, timeout=1)
for i in range(12):
size = 2**i
print(f"Trying with {size} bytes")
sendrecv(s, size)
data = b'ze%s\x96:M#\xd8\x98\x9d\x96\xf5?\x80c\xc6\xa7\x03\xe0i\x04V\xcb\xa3\x95#GC\xabf\x98'
#sendcheck(s, data)
print("All sizes passed.")
if __name__ == "__main__":
main()

View File

@@ -1490,7 +1490,7 @@ def parse_tree(tree, debug=False):
def larkparse(f, debug=False):
with open(GRAMMAR_FILE) as g:
asparser = lark.Lark(g.read())
asparser = lark.Lark(g.read(), maybe_placeholders=False)
data = f.read()
if isinstance(data, bytes):
data = data.decode()

View File

@@ -69,7 +69,7 @@ def dump(secmap):
def parse_args():
parser = argparse.ArgumentParser(description='Assemble.')
parser = argparse.ArgumentParser(description='Link.')
parser.add_argument('--debug', action='store_true',
help='print debug info')
parser.add_argument('objfiles', metavar='O', nargs='+',

17
wave/Makefile Normal file
View File

@@ -0,0 +1,17 @@
all: sim
sim: pdmout_test.ghw square_test.ghw wave_test.ghw
sim_sources = pdmout_test.vhdl square_test.vhdl wave_test.vhdl
sources = pdmout.vhdl square.vhdl wave.vhdl pdm.vhdl
%.ghw: work-obj93.cf
ghdl -r $* --wave=$@
work-obj93.cf: $(sim_sources) $(sources)
ghdl -a $^
PHONY: sim
.PRECIOUS: test.ghw

View File

@@ -1,17 +0,0 @@
all: sim
sim: pdmout_test.ghw square_test.ghw
sim_sources = pdmout_test.vhdl square_test.vhdl
sources = pdmout.vhdl square.vhdl
%.ghw: work-obj93.cf
ghdl -r $* --wave=$@
work-obj93.cf: $(sim_sources) $(sources)
ghdl -a $^
PHONY: sim
.PRECIOUS: test.ghw

46
wave/pdm.vhdl Normal file
View File

@@ -0,0 +1,46 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pdm is
port
(
clk : in std_logic;
rst : in std_logic;
-- hardware
out_pin : out std_logic;
-- input interface
enabled : in std_logic;
sample : in std_logic_vector(15 downto 0)
);
end pdm;
architecture Behavioral of pdm is
signal feedback: signed(16 downto 0);
begin
-- PDM process
-- drives pin_out, feedback
process(clk, rst)
begin
if rst = '1' then
feedback <= to_signed(0, 17);
out_pin <= '0';
elsif rising_edge(clk) and enabled = '1' then
if feedback > 0 then
out_pin <= '1';
feedback <= feedback + signed("0" & sample) - ("0" & x"ffff");
else
out_pin <= '0';
feedback <= feedback + signed("0" & sample);
end if;
end if;
end process;
end Behavioral;

175
wave/wave.vhdl Normal file
View File

@@ -0,0 +1,175 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- some kind of square wave generator, with PDM output
entity wave is
port
(
-- AXI4 slave interface
aclk : in std_logic;
aresetn : in std_logic;
-- read addr
araddr : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
arready : out std_logic;
-- read data
rdata : out std_logic_vector(31 downto 0);
rresp : out std_logic;
rvalid : out std_logic;
rready : in std_logic;
-- write addr
awaddr : in std_logic_vector(31 downto 0);
awvalid : in std_logic;
awready : out std_logic;
-- write data
wdata : in std_logic_vector(31 downto 0);
wstrb : in std_logic_vector(3 downto 0);
-- write resp
bresp : out std_logic;
bvalid : out std_logic;
bready : in std_logic;
-- PDM output!
pdmout : out std_logic
);
end wave;
--
-- Mem layout:
-- 0x00: control: [bit0: enabled]
-- 0x04: 32-bit unsigned period (in clock cycles)
-- 0x08: 16-bit unsigned high value (high 16 bits ignored)
-- 0x0c: 16-bit unsigned low value (high 16 bits ignored)
architecture Behavioral of wave is
component pdm is
port
(
clk : in std_logic;
rst : in std_logic;
-- hardware
out_pin : out std_logic;
-- input interface
enabled : in std_logic;
sample : in std_logic_vector(15 downto 0)
);
end component;
-- all registers
signal period, hi_val, lo_val, sample: std_logic_vector(15 downto 0);
signal enabled, rst, onwrite: std_logic;
signal counter: unsigned(23 downto 0);
begin
arready <= '1';
awready <= '1';
rst <= not aresetn;
pdm0: pdm port map(clk => aclk, rst => rst, out_pin => pdmout,
sample => sample, enabled => enabled);
-- main process
-- drives counter, sample
process(aclk, aresetn)
variable high: std_logic;
begin
if aresetn = '0' then
counter <= to_unsigned(0, 24);
sample <= x"0000";
high := '0';
elsif rising_edge(aclk) then
counter <= to_unsigned(0, 24);
if high = '1' then
sample <= hi_val;
else
sample <= lo_val;
end if;
if enabled = '1' and unsigned(period) /= 0 and onwrite = '0' then
if counter(22 downto 7) = unsigned(period) - 1
and counter(6 downto 0) = x"7f" then
high := not high;
else
counter <= counter + 1;
end if;
end if;
end if;
end process;
-- Bus slave process
-- drives period, value, out_addr, enabled, onwrite
process(aclk, aresetn)
-- 00: control, 01: period, 02: high, 03: low
variable waddr: std_logic_vector(2 downto 0);
variable raddr: std_logic_vector(2 downto 0);
begin
if aresetn = '0' then
period <= x"0000";
hi_val <= x"0000";
lo_val <= x"0000";
enabled <= '0';
waddr := "000";
elsif rising_edge(aclk) then
rvalid <= '0';
rdata <= x"00000000";
rresp <= '0';
bvalid <= '0';
bresp <= '0';
onwrite <= '0';
if arvalid = '1' then
raddr := araddr(4 downto 2);
end if;
if awvalid = '1' then
waddr := awaddr(4 downto 2);
end if;
if arvalid = '1' then
case waddr(1 downto 0) is
when "00" =>
rdata(0) <= enabled;
when "01" =>
rdata(23 downto 8) <= period;
when "10" =>
rdata(15 downto 0) <= hi_val;
when "11" =>
rdata(15 downto 0) <= lo_val;
when others =>
end case;
rvalid <= '1';
end if;
if unsigned(wstrb) > 0 then
case waddr(1 downto 0) is
when "00" =>
enabled <= wdata(0);
when "01" =>
period <= wdata(23 downto 8);
when "10" =>
hi_val <= wdata(15 downto 0);
when "11" =>
lo_val <= wdata(15 downto 0);
when others =>
end case;
bvalid <= '1';
onwrite <= '1';
end if;
end if;
end process;
end Behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity wave_test is
end wave_test;
architecture rtl of wave_test is
component wave is
port
(
-- AXI4 slave interface
aclk : in std_logic;
aresetn : in std_logic;
-- read addr
araddr : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
arready : out std_logic;
-- read data
rdata : out std_logic_vector(31 downto 0);
rresp : out std_logic;
rvalid : out std_logic;
rready : in std_logic;
-- write addr
awaddr : in std_logic_vector(31 downto 0);
awvalid : in std_logic;
awready : out std_logic;
-- write data
wdata : in std_logic_vector(31 downto 0);
wstrb : in std_logic_vector(3 downto 0);
-- write resp
bresp : out std_logic;
bvalid : out std_logic;
bready : in std_logic;
-- PDM output!
pdmout : out std_logic
);
end component;
signal finished, clk, rst, rstn: std_logic := '0';
signal arvalid, arready, awvalid, awready: std_logic;
signal rresp, rvalid, rready, bresp, bvalid, bready: std_logic;
signal wstrb: std_logic_vector(3 downto 0);
signal araddr, rdata, awaddr, wdata: std_logic_vector(31 downto 0);
signal pdmout: std_logic;
constant period: integer := 7 * 256;
constant half_time: time := 1280 ns * period;
begin
rstn <= not rst;
dut: wave port map(aclk => clk, aresetn => rstn,
arvalid => arvalid, arready => arready, awvalid => awvalid, awready => awready,
rresp => rresp, rvalid => rvalid, rready => rready, bresp => bresp, bvalid => bvalid, bready => bready,
wstrb => wstrb, araddr => araddr, rdata => rdata, awaddr => awaddr, wdata => wdata,
pdmout => pdmout
);
-- tick tock
process
begin
if finished = '0' then
clk <= not clk;
wait for 5 ns;
else
clk <= '0';
wait;
end if;
end process;
process
begin
rst <= '1';
arvalid <= '0';
awvalid <= '0';
wstrb <= "0000";
wait for 1 ns;
-- assert(='0') report "Fail rst" severity error;
rst <= '0';
wait for 10 ns;
awvalid <= '1';
awaddr <= x"00000000"; -- enable
wstrb <= "1111";
wdata <= x"00000001";
bready <= '1';
wait for 10 ns;
assert(bvalid = '1') report "Write error" severity error;
assert(bresp = '0') report "Write fail" severity error;
assert(awready = '1') report "Write error" severity error;
awaddr <= x"00000004"; -- period
wdata <= std_logic_vector(to_unsigned(period, 32));
wait for 10 ns;
-- read back
wstrb <= "0000";
awvalid <= '0';
arvalid <= '1';
araddr <= x"00000004";
rready <= '1';
wait for 10 ns;
assert(unsigned(rdata) = period) report "Period readback failed" severity error;
arvalid <= '0';
awvalid <= '1';
wstrb <= "1111";
awaddr <= x"00000008"; -- high
wdata <= x"00008000";
wait for 10 ns;
awaddr <= x"0000000c"; -- low
wdata <= x"00004000";
wait for 10 ns;
wstrb <= "0000";
awvalid <= '0';
wait for 30 ns;
assert(pdmout = '1') report "wrong pdmout" severity error;
wait for 10 ns;
assert(pdmout = '0') report "wrong pdmout" severity error;
wait for 10 ns;
assert(pdmout = '0') report "wrong pdmout" severity error;
wait for 10 ns;
assert(pdmout = '1') report "wrong pdmout" severity error;
wait for 10 ns;
assert(pdmout = '0') report "wrong pdmout" severity error;
wait for 10 ns;
assert(pdmout = '0') report "wrong pdmout" severity error;
wait for 10 ns;
assert(pdmout = '0') report "wrong pdmout" severity error;
wait for 10 ns;
assert(pdmout = '1') report "wrong pdmout" severity error;
wait for 100 us;
assert false report "Test done." severity note;
finished <= '1';
wait;
end process;
end rtl;