Commit Graph

7 Commits

Author SHA1 Message Date
Paul Mathieu
36bc1417b6 cpu: more instruction pipelining
This is needed to make WNS room for fetching instructions from SRAM.
2021-04-17 23:02:58 -07:00
Paul Mathieu
b70cdd13c4 Add partial support for 8-bit loads
We're big-endian.
when we have this in memory:

00 01 02 03

And we need the first byte, we load the first 16-bit word:

0x0001

The first byte is then in the upper part of the word, and requires
a right shift by 8.
So any load into an 8-bit typed container needs to shift stuff.

So far, stores from/to the stack are exempted, they always load/store
full 16-bit words.

And a few othe rminor things. Like string null terminators.
And escaped characters in character literals.

Can you believe it's spelled 'literal', with a single t?
Me neither.
2021-03-18 08:35:23 -07:00
Paul Mathieu
7ba6746ddd cpu: streamline hold a little 2021-03-14 18:08:13 -07:00
Paul Mathieu
d1d0e421ce cpu: make BEQ and BNEQ only PC-relative 2021-03-14 12:14:29 -07:00
Paul Mathieu
24c6831813 Small fixes for synthesis 2021-03-13 21:02:54 -08:00
Paul Mathieu
1e6dc25c88 cpu: wait when mem_busy is high 2021-03-06 19:11:11 -08:00
Paul Mathieu
634596fd0f Exctract cpu into its own module 2021-03-06 16:37:42 -08:00