diff --git a/dsp/dsp.vhdl b/dsp/dsp.vhdl index fa9e2f2..f201d12 100644 --- a/dsp/dsp.vhdl +++ b/dsp/dsp.vhdl @@ -11,10 +11,13 @@ entity dsp is led: out std_logic_vector(7 downto 0); - uart_rx: in std_logic; - uart_tx: out std_logic; + uart0_rx: in std_logic; + uart0_tx: out std_logic; - pdmout0_pin: out std_logic + pdmout0_pin: out std_logic; + + uart1_rx: in std_logic; + uart1_tx: out std_logic ); end dsp; @@ -72,6 +75,11 @@ architecture rtl of dsp is end component; component uart is + generic + ( + baudrate : in natural := 1_000_000 + ); + port ( clk : in std_logic; @@ -162,8 +170,10 @@ architecture rtl of dsp is signal mem_doutb, mem_addrb: std_logic_vector(15 downto 0); signal rom_data_addr, rom_data_out: std_logic_vector(15 downto 0); - signal uart_din, uart_dout, uart_addr: std_logic_vector(15 downto 0); - signal uart_we, uart_re: std_logic; + signal uart0_din, uart0_dout, uart0_addr: std_logic_vector(15 downto 0); + signal uart0_we, uart0_re: std_logic; + signal uart1_din, uart1_dout, uart1_addr: std_logic_vector(15 downto 0); + signal uart1_we, uart1_re: std_logic; signal cpu_write, cpu_read, cpu_busy: std_logic; signal cpu_mosi, cpu_miso, cpu_addr: std_logic_vector(15 downto 0); @@ -196,9 +206,13 @@ begin addra => mem_addra, wea => mem_wea, dina => mem_dina, douta => mem_douta, addrb => mem_addrb, doutb => mem_doutb); - uart0: uart port map(clk => clk, rst => rst, rx_pin => uart_rx, tx_pin => uart_tx, - addr => uart_addr, din => uart_din, dout => uart_dout, - re => uart_re, we => uart_we); + uart0: uart port map(clk => clk, rst => rst, rx_pin => uart0_rx, tx_pin => uart0_tx, + addr => uart0_addr, din => uart0_din, dout => uart0_dout, + re => uart0_re, we => uart0_we); + uart1: uart generic map(baudrate => 31250) + port map(clk => clk, rst => rst, rx_pin => uart1_rx, tx_pin => uart1_tx, + addr => uart1_addr, din => uart1_din, dout => uart1_dout, + re => uart1_re, we => uart1_we); square0: square port map(clk => clk, rst => rst, s_we => square0_s_we, s_addr => square0_s_addr, s_din => square0_s_din, @@ -225,9 +239,10 @@ begin -- 0x0000 - 0x0fff ROM -- 0x1000 - 0x1fff RAM -- 0xc000 - 0xc00f LED0 - -- 0xc010 - 0xc01f UART0 + -- 0xc010 - 0xc01f UART0 (1 Mbaud) -- 0xc020 - 0xc02f PDMOUT0 -- 0xc030 - 0xc03f SQUARE0 + -- 0xc040 - 0xc04f UART1 (31250 baud) led <= led_r; @@ -263,11 +278,12 @@ begin mem_addra <= x"0" & dbus_addr(11 downto 0); rom_data_addr <= x"0" & dbus_addr(11 downto 0); - uart_addr <= x"000" & dbus_addr(3 downto 0); + uart0_addr <= x"000" & dbus_addr(3 downto 0); + uart1_addr <= x"000" & dbus_addr(3 downto 0); pdmout0_addr <= x"000" & dbus_addr(3 downto 0); square0_s_addr <= x"000" & dbus_addr(3 downto 0); - process(dbus_addr, dbus_mosi, dbus_write, mem_douta, rst, rom_data_out, led_r, dbus_read, uart_dout) + process(dbus_addr, dbus_mosi, dbus_write, mem_douta, rst, rom_data_out, led_r, dbus_read, uart0_dout, uart1_dout) begin dbus_miso <= x"0000"; @@ -276,9 +292,13 @@ begin led_next <= led_r; - uart_din <= dbus_mosi; - uart_we <= '0'; - uart_re <= '0'; + uart0_din <= dbus_mosi; + uart0_we <= '0'; + uart0_re <= '0'; + + uart1_din <= dbus_mosi; + uart1_we <= '0'; + uart1_re <= '0'; pdmout0_we <= '0'; pdmout0_din <= dbus_mosi; @@ -299,13 +319,17 @@ begin led_next <= dbus_mosi(7 downto 0); end if; when x"1" => -- UART0 - dbus_miso <= uart_dout; - uart_we <= dbus_write; - uart_re <= dbus_read; + dbus_miso <= uart0_dout; + uart0_we <= dbus_write; + uart0_re <= dbus_read; when x"2" => -- PDMOUT0 pdmout0_we <= dbus_write; when x"3" => -- SQUARE0 square0_s_we <= dbus_write; + when x"4" => -- UART1 + dbus_miso <= uart1_dout; + uart1_we <= dbus_write; + uart1_re <= dbus_read; when others => end case; when others => diff --git a/dsp/dsp_test.vhdl b/dsp/dsp_test.vhdl index 79a3269..638a7dc 100644 --- a/dsp/dsp_test.vhdl +++ b/dsp/dsp_test.vhdl @@ -18,10 +18,13 @@ architecture rtl of dsp_test is led: out std_logic_vector(7 downto 0); - uart_rx: in std_logic; - uart_tx: out std_logic; + uart0_rx: in std_logic; + uart0_tx: out std_logic; - pdmout0_pin: out std_logic + pdmout0_pin: out std_logic; + + uart1_rx: in std_logic; + uart1_tx: out std_logic ); end component; diff --git a/dsp/makefile b/dsp/makefile index 57a1cbc..134bc5e 100644 --- a/dsp/makefile +++ b/dsp/makefile @@ -10,12 +10,13 @@ CFLAGS = -I../wave -I../uart offset = $(shell printf "%d" 0x1100) -test_boot_rom.gen.vhdl: main.o ../uart/uart.o +test_boot_rom.gen.vhdl: bootloader.o ../uart/uart.o boot_rom.gen.vhdl: bootloader.o ../uart/uart.o -hello.bin: hello.o ../uart/uart.o - -synth.bin: main.o ../uart/uart.o +# hello.bin: hello.o ../uart/uart.o +# synth.bin: synth.o ../uart/uart.o +# echo.bin: echo.o ../uart/uart.o +# bootloader.bin: bootloader.o ../uart/uart.o sim_sources = dsp_test.vhdl test_boot_rom.gen.vhdl sources = dsp.vhdl ram.vhdl \ @@ -31,7 +32,7 @@ sources = dsp.vhdl ram.vhdl \ ../lab/dsp/au_base_project.runs/synth_1/runme.sh -%.bin: +%.bin: %.o ../uart/uart.o $(LD) -o $@ --offset $(offset) $^ %.gen.vhdl: diff --git a/dsp/sys.h b/dsp/sys.h index d07c08e..65cec29 100644 --- a/dsp/sys.h +++ b/dsp/sys.h @@ -8,8 +8,10 @@ #define UART0_BASE 0xc010 #define PDMOUT0_BASE 0xc020 #define SQUARE0_BASE 0xc030 +#define UART1_BASE 0xc040 #define led0 ((struct led*) LED0_BASE) #define uart0 ((struct uart*) UART0_BASE) +#define uart1 ((struct uart*) UART1_BASE) #define pdmout0 ((struct pdmout*) PDMOUT0_BASE) #define square0 ((struct square*) SQUARE0_BASE)