diff --git a/arm/app.ld b/arm/app.ld
index 3820254..7a4cbca 100644
--- a/arm/app.ld
+++ b/arm/app.ld
@@ -3,6 +3,8 @@ MEMORY
     ICTM (rwx) : ORIGIN = 0x00000800, LENGTH = 14336
 }
 
+_vector_table = 0x0;
+
 SECTIONS
 {
     .text :
diff --git a/arm/main.cc b/arm/main.cc
index 89c31b7..5b22ef2 100644
--- a/arm/main.cc
+++ b/arm/main.cc
@@ -8,6 +8,8 @@
 #include "uart.h"
 #include "uart_async.h"
 
+extern volatile uint32_t _vector_table[];
+
 namespace {
 using async::AwaitableType;
 
@@ -24,20 +26,17 @@ void Timer0Isr() {
 void SetupUart() {
     InitUarts();
 
-    auto* vector_table = reinterpret_cast<uint32_t*>(0x0);
-    vector_table[16 + HardFault_IRQn] =
-        reinterpret_cast<uint32_t>(crash::HardFaultHandler);
-
-    vector_table[16 + Uart0_IRQn] = reinterpret_cast<uint32_t>(Uart0Isr);
-    vector_table[16 + Timer0_IRQn] = reinterpret_cast<uint32_t>(Timer0Isr);
+    _vector_table[16 + Uart0_IRQn] = reinterpret_cast<uint32_t>(Uart0Isr);
     NVIC_SetPriority(Uart0_IRQn, 3);
     NVIC_EnableIRQ(Uart0_IRQn);
 }
 
 void SetupTimer() {
-    NVIC_EnableIRQ(Timer0_IRQn);
     timer0->SetupAsWdt(100000 * 4000);
     timer0->EnableT1();
+
+    _vector_table[16 + Timer0_IRQn] = reinterpret_cast<uint32_t>(Timer0Isr);
+    NVIC_EnableIRQ(Timer0_IRQn);
 }
 
 async::task<> echo() {
@@ -49,6 +48,9 @@ async::task<> echo() {
 }  // namespace
 
 int main() {
+    _vector_table[16 + HardFault_IRQn] =
+        reinterpret_cast<uint32_t>(crash::HardFaultHandler);
+
     SetupUart();
     SetupTimer();