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dsp: refactor test

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This commit is contained in:
Paul Mathieu 2021-04-24 08:57:55 -07:00
parent 71212cde2d
commit 67634ca178
3 changed files with 32 additions and 39 deletions
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62
dsp/dsp_test.vhdl
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@ -41,6 +41,25 @@ architecture rtl of dsp_test is
constant UART_PERIOD: time := 1000 ns; constant UART_PERIOD: time := 1000 ns;
procedure uart_send(
signal s: in str;
signal o: out std_logic
) is
begin
for i in s'range loop
o <= '0'; -- start bit
wait for UART_PERIOD;
for j in 0 to 7 loop
o <= s(i)(j);
wait for UART_PERIOD;
end loop;
o <= '1'; -- stop bit
wait for UART_PERIOD;
end loop;
end procedure;
begin begin
dut: dsp port map(clk => clk, rst => rst, dut: dsp port map(clk => clk, rst => rst,
led => led, uart_rx => uart_rx, uart_tx => uart_tx, led => led, uart_rx => uart_rx, uart_tx => uart_tx,
@ -60,42 +79,15 @@ begin
rst <= '0'; rst <= '0';
wait for 20 us; -- wait for 20 us;
for i in 0 to 7 loop -- uart_send(prog, uart_rx);
uart_rx <= '0'; -- start bit -- wait for 2 us;
wait for UART_PERIOD; -- assert(led = x"f0") report "Fail prog" severity error;
-- uart_send(jump, uart_rx);
-- wait for 2 us;
-- assert(led = x"01") report "Fail prog" severity error;
for j in 0 to 7 loop wait for 200 us;
uart_rx <= prog(i)(j);
wait for UART_PERIOD;
end loop;
uart_rx <= '1'; -- stop bit
wait for UART_PERIOD;
end loop;
wait for 2 us;
assert(led = x"f0") report "Fail prog" severity error;
for i in 0 to 2 loop
uart_rx <= '0'; -- start bit
wait for UART_PERIOD;
for j in 0 to 7 loop
uart_rx <= jump(i)(j);
wait for UART_PERIOD;
end loop;
uart_rx <= '1'; -- stop bit
wait for UART_PERIOD;
end loop;
wait for 2 us;
assert(led = x"01") report "Fail prog" severity error;
assert false report "Test done." severity note; assert false report "Test done." severity note;

2
dsp/main.c
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@ -41,7 +41,7 @@ int main() {
log("E4\r\n"); log("E4\r\n");
led0->output = 4; led0->output = 4;
} else if (c == 'f') { } else if (c == 'f') {
period = 1119; // F4, 249.23 Hz, maybe period = 1119; // F4, 349.23 Hz, maybe
log("F4\r\n"); log("F4\r\n");
led0->output = 8; led0->output = 8;
} else if (c == 'g') { } else if (c == 'g') {

7
dsp/makefile
View File

@ -10,14 +10,15 @@ CFLAGS = -I../wave -I../uart
offset = $(shell printf "%d" 0x1100) offset = $(shell printf "%d" 0x1100)
test_boot_rom.gen.vhdl: main.o ../uart/uart.o
boot_rom.gen.vhdl: bootloader.o ../uart/uart.o boot_rom.gen.vhdl: bootloader.o ../uart/uart.o
hello.bin: hello.o ../uart/uart.o hello.bin: hello.o ../uart/uart.o
synth.bin: main.o ../uart/uart.o synth.bin: main.o ../uart/uart.o
sim_sources = dsp_test.vhdl sim_sources = dsp_test.vhdl test_boot_rom.gen.vhdl
sources = boot_rom.gen.vhdl dsp.vhdl ram.vhdl \ sources = dsp.vhdl ram.vhdl \
../cpu/cpu.vhdl ../cpu/reg.vhdl ../cpu/alu.vhdl \ ../cpu/cpu.vhdl ../cpu/reg.vhdl ../cpu/alu.vhdl \
$(wildcard ../wave/*.vhdl) \ $(wildcard ../wave/*.vhdl) \
$(wildcard ../sysbus/*.vhdl) \ $(wildcard ../sysbus/*.vhdl) \
@ -26,7 +27,7 @@ sources = boot_rom.gen.vhdl dsp.vhdl ram.vhdl \
../lab/dsp/au_base_project.runs/impl_1/au_top.bin: ../lab/dsp/au_base_project.runs/synth_1/au_top.dcp ../lab/dsp/au_base_project.runs/impl_1/au_top.bin: ../lab/dsp/au_base_project.runs/synth_1/au_top.dcp
../lab/dsp/au_base_project.runs/impl_1/runme.sh ../lab/dsp/au_base_project.runs/impl_1/runme.sh
../lab/dsp/au_base_project.runs/synth_1/au_top.dcp: $(sources) ../lab/dsp/au_base_project.runs/synth_1/au_top.dcp: $(sources) boot_rom.gen.vhdl
../lab/dsp/au_base_project.runs/synth_1/runme.sh ../lab/dsp/au_base_project.runs/synth_1/runme.sh