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dsp: refactor test

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This commit is contained in:
Paul Mathieu
2021-04-24 08:57:55 -07:00
parent 71212cde2d
commit 67634ca178
3 changed files with 32 additions and 39 deletions
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62
dsp/dsp_test.vhdl
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@@ -41,6 +41,25 @@ architecture rtl of dsp_test is
constant UART_PERIOD: time := 1000 ns;
procedure uart_send(
signal s: in str;
signal o: out std_logic
) is
begin
for i in s'range loop
o <= '0'; -- start bit
wait for UART_PERIOD;
for j in 0 to 7 loop
o <= s(i)(j);
wait for UART_PERIOD;
end loop;
o <= '1'; -- stop bit
wait for UART_PERIOD;
end loop;
end procedure;
begin
dut: dsp port map(clk => clk, rst => rst,
led => led, uart_rx => uart_rx, uart_tx => uart_tx,
@@ -60,42 +79,15 @@ begin
rst <= '0';
wait for 20 us;
for i in 0 to 7 loop
uart_rx <= '0'; -- start bit
wait for UART_PERIOD;
-- wait for 20 us;
-- uart_send(prog, uart_rx);
-- wait for 2 us;
-- assert(led = x"f0") report "Fail prog" severity error;
-- uart_send(jump, uart_rx);
-- wait for 2 us;
-- assert(led = x"01") report "Fail prog" severity error;
for j in 0 to 7 loop
uart_rx <= prog(i)(j);
wait for UART_PERIOD;
end loop;
uart_rx <= '1'; -- stop bit
wait for UART_PERIOD;
end loop;
wait for 2 us;
assert(led = x"f0") report "Fail prog" severity error;
for i in 0 to 2 loop
uart_rx <= '0'; -- start bit
wait for UART_PERIOD;
for j in 0 to 7 loop
uart_rx <= jump(i)(j);
wait for UART_PERIOD;
end loop;
uart_rx <= '1'; -- stop bit
wait for UART_PERIOD;
end loop;
wait for 2 us;
assert(led = x"01") report "Fail prog" severity error;
wait for 200 us;
assert false report "Test done." severity note;