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Word-precise imm for BEQ and BNEQ

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Paul Mathieu
2021-02-22 20:33:05 -08:00
parent f59b3efb9f
commit 64d440c94b
2 changed files with 4 additions and 4 deletions
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4
first/cpu.vhdl
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@@ -167,14 +167,14 @@ begin
when "1101" => -- BEQ [rn, imm] (jump to [rn, imm] if flag is set, imm is signed 8 bits)
if reg_q(15)(0) = '1' then
reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0)));
reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0) & '0'));
cpu_state_next <= BRANCH;
end if;
when "1110" => -- SET rd, imm (rd := imm, imm is 8 bit)
reg_d(regn_0) <= x"00" & inst(7 downto 0);
when "1111" => -- BNEQ [rn, imm]
if reg_q(15)(0) = '0' then
reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0)));
reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0) & '0'));
cpu_state_next <= BRANCH;
end if;