Exctract cpu into its own module
This commit is contained in:
Paul Mathieu
parent
9e61fd9456
commit
634596fd0f
70
cpu/alu.vhdl
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70
cpu/alu.vhdl
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@ -0,0 +1,70 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity alu is
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port(
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a: in std_logic_vector(15 downto 0);
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b: in std_logic_vector(15 downto 0);
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sel: in std_logic_vector(3 downto 0);
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flag: out std_logic;
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q: out std_logic_vector(15 downto 0)
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);
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end alu;
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architecture behavior of alu is
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begin
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process(a, b, sel) is
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variable tmp: std_logic_vector(31 downto 0);
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variable idx: natural;
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begin
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q <= x"0000";
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flag <= '0';
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tmp := x"00000000";
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idx := 0;
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case sel is
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when "0011" => -- q = a + b, flag is carry
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tmp(16 downto 0) := std_logic_vector(unsigned('0' & a) + unsigned(b));
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q <= tmp(15 downto 0);
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flag <= tmp(16);
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when "0100" => -- q = a - b, flag if a < b
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tmp(16 downto 0) := std_logic_vector(unsigned('1' & a) - unsigned(b));
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q <= tmp(15 downto 0);
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flag <= not tmp(16);
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when "0101" => q <= a or b;
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when "0110" => q <= a and b;
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when "0111" => q <= not a;
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when "1000" => q <= a xor b;
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when "1001" => -- left shift by 1
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q <= a(14 downto 0) & '0';
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flag <= a(15);
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when "1010" => -- right shift by b(3 downto 0)
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idx := to_integer(unsigned(b(3 downto 0)));
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tmp(15 - idx downto 0) := a(15 downto idx);
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q <= tmp(15 downto 0);
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flag <= a(0);
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when "1011" => -- q = a * b
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--tmp := std_logic_vector(unsigned(a) * unsigned(b));
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q <= tmp(15 downto 0);
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when "1100" => -- flag if a = b
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if (a = b) then
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flag <= '1';
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else
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flag <= '0';
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end if;
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--- room for a few more things:
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-- - rotate
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-- - not / nand
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-- - gt...
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when others =>
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-- do nothing
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end case;
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end process;
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end behavior;
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197
cpu/cpu.vhdl
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197
cpu/cpu.vhdl
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@ -0,0 +1,197 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity cpu is
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port(
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clk: in std_logic;
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rst: in std_logic;
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code_data: in std_logic_vector(15 downto 0);
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code_addr: out std_logic_vector(15 downto 0);
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mem_in: in std_logic_vector(15 downto 0);
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mem_out: out std_logic_vector(15 downto 0);
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mem_addr: out std_logic_vector(15 downto 0);
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mem_write: out std_logic;
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mem_read: out std_logic
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);
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end entity cpu;
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architecture behavior of cpu is
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component alu is
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port(
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a: in std_logic_vector(15 downto 0);
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b: in std_logic_vector(15 downto 0);
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sel: in std_logic_vector(3 downto 0);
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flag: out std_logic;
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q: out std_logic_vector(15 downto 0)
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);
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end component;
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component reg is
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port(
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clk : in std_logic;
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rst : in std_logic;
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d : in std_logic_vector(15 downto 0);
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q : out std_logic_vector(15 downto 0)
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);
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end component;
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signal alu_a: std_logic_vector(15 downto 0);
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signal alu_b: std_logic_vector(15 downto 0);
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signal alu_q: std_logic_vector(15 downto 0);
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signal alu_sel: std_logic_vector(3 downto 0);
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signal alu_flag: std_logic;
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signal load_reg_next, load_reg: std_logic_vector(15 downto 0);
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signal load_addr_next, load_addr: std_logic_vector(15 downto 0);
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type regbank is array(0 to 15) of std_logic_vector(15 downto 0);
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signal reg_d: regbank;
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signal reg_q: regbank;
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type cpu_state_t is (RUN, LOAD, BRANCH);
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signal cpu_state, cpu_state_next: cpu_state_t;
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begin
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cpu_alu: alu port map(a => alu_a, b => alu_b, sel => alu_sel, flag => alu_flag, q => alu_q);
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load_reg_r: reg port map(clk => clk, rst => rst, d => load_reg_next, q => load_reg);
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load_addr_r: reg port map(clk => clk, rst => rst, d => load_addr_next, q => load_addr);
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allregs:
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for i in 0 to 15 generate
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regx: reg port map(clk => clk, rst => rst, d => reg_d(i), q => reg_q(i));
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end generate allregs;
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process(clk, rst)
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begin
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if rst = '1' then
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cpu_state <= BRANCH; -- wait a cycle at first
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elsif rising_edge(clk) then
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cpu_state <= cpu_state_next;
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end if;
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end process;
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code_addr <= reg_q(14);
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process(code_data, reg_q, mem_in, alu_q, alu_flag, cpu_state, load_addr, load_reg) is
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variable inst: std_logic_vector(15 downto 0);
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variable regn_0: natural;
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variable regn_1: natural;
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variable regn_2: natural;
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variable do_alu: std_logic;
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begin
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mem_write <= '0';
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mem_read <= '0';
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mem_addr <= x"0000";
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mem_out <= x"0000";
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alu_sel <= "0000";
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alu_a <= x"0000";
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alu_b <= x"0000";
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do_alu := '0';
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for i in 0 to 15 loop
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reg_d(i) <= reg_q(i);
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end loop;
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cpu_state_next <= RUN;
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load_reg_next <= load_reg;
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load_addr_next <= load_addr;
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case cpu_state is
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when RUN =>
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reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
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inst := code_data;
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when LOAD =>
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inst := x"0000"; -- NOP
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mem_addr <= load_addr; -- maintain this until we're done reading
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if load_reg(3 downto 0) = x"e" then
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cpu_state_next <= BRANCH;
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else
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reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
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end if;
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regn_0 := to_integer(unsigned(load_reg(3 downto 0)));
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reg_d(regn_0) <= mem_in;
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when BRANCH =>
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inst := x"0000"; -- NOP
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reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
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end case;
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regn_0 := to_integer(unsigned(inst(11 downto 8)));
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regn_1 := to_integer(unsigned(inst(7 downto 4)));
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regn_2 := to_integer(unsigned(inst(3 downto 0)));
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case inst(15 downto 12) is
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when "0000" => -- NOP
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when "0001" => -- LOAD rn, [rm, imm] (imm is signed 4 bits)
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mem_read <= '1';
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cpu_state_next <= LOAD;
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reg_d(14) <= reg_q(14); -- halt the prefetcher
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load_addr_next <= std_logic_vector(signed(reg_q(regn_1)) + signed(inst(3 downto 0) & '0'));
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mem_addr <= std_logic_vector(signed(reg_q(regn_1)) + signed(inst(3 downto 0) & '0'));
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load_reg_next(3 downto 0) <= inst(11 downto 8);
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when "0010" => -- STORE rn, [rm, imm]
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mem_write <= '1';
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mem_addr <= std_logic_vector(signed(reg_q(regn_1)) + signed(inst(3 downto 0) & '0'));
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mem_out <= reg_q(regn_0);
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--- ALU stuff
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when "0011" => do_alu := '1'; -- ADD rd, rn, rm (rd := rn + rm)
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when "0100" => do_alu := '1'; -- SUB rd, rn, rm (rd := rn - rm)
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when "0101" => do_alu := '1'; -- OR rd, rn, rm (rd := rn or rm)
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when "0110" => do_alu := '1'; -- AND rd, rn, rm (rd := rn and rm)
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when "0111" => do_alu := '1'; -- NOT rd, rn (rd := not rn)
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when "1000" => do_alu := '1'; -- XOR rd, rn, rm (rd := rn xor rm)
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when "1001" => -- SETH rd, imm
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reg_d(regn_0)(15 downto 8) <= inst(7 downto 0);
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when "1010" => -- SHR rd, rn, imm (rd := rn >> imm)
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alu_sel <= inst(15 downto 12);
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alu_a <= reg_q(regn_1);
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alu_b <= x"000" & inst(3 downto 0);
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reg_d(regn_0) <= alu_q;
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when "1011" => do_alu := '1'; -- MUL rd, rn, rm (rd := rn * rm)
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when "1100" => -- CMP rn, rm (flag := 1 if equal)
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alu_sel <= "1100";
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alu_a <= reg_q(regn_0);
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alu_b <= reg_q(regn_1);
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reg_d(15)(0) <= alu_flag;
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when "1101" => -- BEQ [rn, imm] (jump to [rn, imm] if flag is set, imm is signed 8 bits)
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if reg_q(15)(0) = '1' then
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reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0) & '0'));
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cpu_state_next <= BRANCH;
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end if;
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when "1110" => -- SET rd, imm (rd := imm, imm is 8 bit)
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reg_d(regn_0) <= x"00" & inst(7 downto 0);
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when "1111" => -- BNEQ [rn, imm]
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if reg_q(15)(0) = '0' then
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reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0) & '0'));
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cpu_state_next <= BRANCH;
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end if;
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when others => -- do nothing
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end case;
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if do_alu = '1' then
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-- 1:1 mapping
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alu_sel <= inst(15 downto 12);
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alu_a <= reg_q(regn_1);
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alu_b <= reg_q(regn_2);
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reg_d(regn_0) <= alu_q;
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reg_d(15)(0) <= alu_flag;
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if inst(11 downto 8) = x"e" then
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cpu_state_next <= BRANCH;
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end if;
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end if;
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end process;
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end behavior;
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123
cpu/cpu_test.vhdl
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123
cpu/cpu_test.vhdl
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@ -0,0 +1,123 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity cpu_test is
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end cpu_test;
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architecture rtl of cpu_test is
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component cpu is port(
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clk: in std_logic;
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rst: in std_logic;
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code_data: in std_logic_vector(15 downto 0);
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code_addr: out std_logic_vector(15 downto 0);
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mem_in: in std_logic_vector(15 downto 0);
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mem_out: out std_logic_vector(15 downto 0);
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mem_addr: out std_logic_vector(15 downto 0);
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mem_write: out std_logic;
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mem_read: out std_logic
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);
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end component;
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type romtype is array(0 to 11) of std_logic_vector(15 downto 0);
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signal romdata: romtype := (
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x"0000", -- NOP
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x"e02a", -- SET r0, 42
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x"e125", -- SET r1, 37
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x"2010", -- STORE r0, [r1]
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x"1210", -- LOAD r2, [r1]
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x"3322", -- ADD r3, r2, r2
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x"2310", -- STORE r3, [r1]
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x"c020", -- CMP r0, r2
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x"de01", -- BEQ pc, 2
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x"0000", -- NOP
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x"ee00", -- SET pc, 0
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x"0000"
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);
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signal finished, clk, rst: std_logic := '0';
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signal mem_write, mem_read: std_logic;
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signal rom_data, rom_addr, mem_in, mem_out, mem_addr: std_logic_vector(15 downto 0);
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begin
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dut: cpu port map(clk => clk, rst => rst,
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code_data => rom_data, code_addr => rom_addr,
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mem_in => mem_in, mem_out => mem_out, mem_addr => mem_addr,
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mem_write => mem_write, mem_read => mem_read);
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-- clock
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process
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begin
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if finished = '0' then
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clk <= not clk;
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wait for 5 ns;
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else
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clk <= '0';
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wait;
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end if;
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end process;
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-- rom
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process(clk) is
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variable code_index: natural;
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variable data_index: natural;
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constant alignment: positive := 16 / 8;
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begin
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if rising_edge(clk) then
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code_index := to_integer(unsigned(rom_addr)) / alignment;
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rom_data <= romdata(code_index);
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end if;
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end process;
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process(rom_addr)
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constant alignment: positive := 16 / 8;
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variable index: natural;
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begin
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end process;
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process
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begin
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rst <= '1';
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wait for 1 ns;
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assert(rom_addr=x"0000") report "Fail rst" severity error;
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rst <= '0';
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wait for 10 ns;
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assert(rom_addr=x"0002") report "Fail PC advance @00" severity error;
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wait for 30 ns;
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assert(rom_addr=x"0008") report "Fail PC @06" severity error;
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assert(mem_write='1') report "Fail set mem_write to 1" severity error;
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assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
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assert(mem_out=x"002a") report "Fail set mem_out to 42" severity error;
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wait for 10 ns;
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assert(rom_addr=x"000a") report "Fail PC @08" severity error;
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assert(mem_write='0') report "Fail set mem_write to 0" severity error;
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assert(mem_read='1') report "Fail set mem_read to 1" severity error;
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assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
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mem_in <= x"002a";
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wait for 30 ns;
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assert(rom_addr=x"000e") report "Fail PC @0c" severity error;
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assert(mem_write='1') report "Fail set mem_write to 1" severity error;
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assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
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assert(mem_out=x"0054") report "Fail set mem_out to 84" severity error;
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wait for 40 ns;
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assert(rom_addr=x"0016") report "Fail to branch" severity error;
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wait for 10 ns;
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assert(rom_addr=x"0000") report "Fail to jump" severity error;
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assert false report "Test done." severity note;
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finished <= '1';
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wait;
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end process;
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end rtl;
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18
cpu/makefile
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18
cpu/makefile
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@ -0,0 +1,18 @@
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all: sim
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sim: test.ghw
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sim_sources = cpu_test.vhdl
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sources = cpu.vhdl alu.vhdl reg.vhdl
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test_entity = cpu_test
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test.ghw: work-obj93.cf
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ghdl -r $(test_entity) --wave=$@
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work-obj93.cf: $(sim_sources) $(sources)
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ghdl -a $^
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PHONY: sim
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.PRECIOUS: test.ghw
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55
cpu/reg.vhdl
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55
cpu/reg.vhdl
Normal file
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 02/13/2021 01:13:18 PM
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-- Design Name:
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-- Module Name: register - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity reg is
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Port ( d : in STD_LOGIC_VECTOR (15 downto 0);
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q : out STD_LOGIC_VECTOR (15 downto 0);
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rst : in STD_LOGIC;
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clk : in STD_LOGIC);
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end reg;
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architecture Behavioral of reg is
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begin
|
||||
|
||||
process(clk, rst) is
|
||||
begin
|
||||
if (rst = '1') then
|
||||
q <= x"0000";
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
q <= d;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
Loading…
Reference in New Issue
Block a user