Exctract cpu into its own module

cpu/reg.vhdl

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 02/13/2021 01:13:18 PM
+-- Design Name: 
+-- Module Name: register - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity reg is
+    Port ( d : in STD_LOGIC_VECTOR (15 downto 0);
+           q : out STD_LOGIC_VECTOR (15 downto 0);
+           rst : in STD_LOGIC;
+           clk : in STD_LOGIC);
+end reg;
+
+architecture Behavioral of reg is
+begin
+
+  process(clk, rst) is
+  begin
+    if (rst = '1') then
+      q <= x"0000";
+    else
+      if rising_edge(clk) then
+        q <= d;
+      end if;
+    end if;
+  end process;
+
+end Behavioral;