Exctract cpu into its own module

cpu/cpu_test.vhdl

@@ -0,0 +1,123 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+entity cpu_test is
+end cpu_test;
+
+architecture rtl of cpu_test is
+
+  component cpu is port(
+                         clk: in std_logic;
+                         rst: in std_logic;
+
+                         code_data: in std_logic_vector(15 downto 0);
+                         code_addr: out std_logic_vector(15 downto 0);
+
+                         mem_in: in std_logic_vector(15 downto 0);
+                         mem_out: out std_logic_vector(15 downto 0);
+                         mem_addr: out std_logic_vector(15 downto 0);
+                         mem_write: out std_logic;
+                         mem_read: out std_logic
+                       );
+  end component;
+
+  type romtype is array(0 to 11) of std_logic_vector(15 downto 0);
+  signal romdata: romtype := (
+    x"0000", -- NOP
+    x"e02a", -- SET r0, 42
+    x"e125", -- SET r1, 37
+    x"2010", -- STORE r0, [r1]
+    x"1210", -- LOAD r2, [r1]
+    x"3322", -- ADD r3, r2, r2
+    x"2310", -- STORE r3, [r1]
+    x"c020", -- CMP r0, r2
+    x"de01", -- BEQ pc, 2
+    x"0000", -- NOP
+    x"ee00", -- SET pc, 0
+    x"0000"
+  );
+
+  signal finished, clk, rst: std_logic := '0';
+  signal mem_write, mem_read: std_logic;
+  signal rom_data, rom_addr, mem_in, mem_out, mem_addr: std_logic_vector(15 downto 0);
+
+begin
+  dut: cpu port map(clk => clk, rst => rst,
+                    code_data => rom_data, code_addr => rom_addr,
+                    mem_in => mem_in, mem_out => mem_out, mem_addr => mem_addr,
+                    mem_write => mem_write, mem_read => mem_read);
+
+  -- clock
+  process
+  begin
+    if finished = '0' then
+      clk <= not clk;
+      wait for 5 ns;
+    else
+      clk <= '0';
+      wait;
+    end if;
+  end process;
+
+  -- rom
+  process(clk) is
+    variable code_index: natural;
+    variable data_index: natural;
+    constant alignment: positive := 16 / 8;
+  begin
+    if rising_edge(clk) then
+      code_index := to_integer(unsigned(rom_addr)) / alignment;
+      rom_data <= romdata(code_index);
+    end if;
+  end process;
+
+  process(rom_addr)
+    constant alignment: positive := 16 / 8;
+    variable index: natural;
+  begin
+  end process;
+
+  process
+  begin
+    rst <= '1';
+
+    wait for 1 ns;
+    assert(rom_addr=x"0000") report "Fail rst" severity error;
+
+    rst <= '0';
+
+    wait for 10 ns;
+    assert(rom_addr=x"0002") report "Fail PC advance @00" severity error;
+
+    wait for 30 ns;
+    assert(rom_addr=x"0008") report "Fail PC @06" severity error;
+    assert(mem_write='1') report "Fail set mem_write to 1" severity error;
+    assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
+    assert(mem_out=x"002a") report "Fail set mem_out to 42" severity error;
+
+    wait for 10 ns;
+    assert(rom_addr=x"000a") report "Fail PC @08" severity error;
+    assert(mem_write='0') report "Fail set mem_write to 0" severity error;
+    assert(mem_read='1') report "Fail set mem_read to 1" severity error;
+    assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
+    mem_in <= x"002a";
+
+    wait for 30 ns;
+    assert(rom_addr=x"000e") report "Fail PC @0c" severity error;
+    assert(mem_write='1') report "Fail set mem_write to 1" severity error;
+    assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
+    assert(mem_out=x"0054") report "Fail set mem_out to 84" severity error;
+
+    wait for 40 ns;
+    assert(rom_addr=x"0016") report "Fail to branch" severity error;
+
+    wait for 10 ns;
+    assert(rom_addr=x"0000") report "Fail to jump" severity error;
+
+    assert false report "Test done." severity note;
+    finished <= '1';
+    wait;
+  end process;
+end rtl;