wave: axi4-compliant wave

wave/pdm.vhdl

@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pdm is
+  port
+  (
+    clk     : in std_logic;
+    rst     : in std_logic;
+
+    -- hardware
+    out_pin  : out std_logic;
+
+    -- input interface
+    enabled : in std_logic;
+    sample  : in std_logic_vector(15 downto 0)
+  );
+end pdm;
+
+architecture Behavioral of pdm is
+
+  signal feedback: signed(16 downto 0);
+
+begin
+
+  -- PDM process
+  -- drives pin_out, feedback
+  process(clk, rst)
+  begin
+
+    if rst = '1' then
+      feedback <= to_signed(0, 17);
+      out_pin <= '0';
+    elsif rising_edge(clk) and enabled = '1' then
+      if feedback > 0 then
+        out_pin <= '1';
+        feedback <= feedback + signed("0" & sample) - ("0" & x"ffff");
+      else
+        out_pin <= '0';
+        feedback <= feedback + signed("0" & sample);
+      end if;
+    end if;
+
+  end process;
+
+end Behavioral;