cpu: more instruction pipelining
This is needed to make WNS room for fetching instructions from SRAM.
This commit is contained in:
Paul Mathieu
parent
6825ce464f
commit
36bc1417b6
28
cpu/cpu.vhdl
28
cpu/cpu.vhdl
@ -49,7 +49,7 @@ architecture behavior of cpu is
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signal load_reg_next, load_reg: std_logic_vector(15 downto 0);
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signal load_addr_next, load_addr: std_logic_vector(15 downto 0);
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signal hold_inst_next, hold_inst: std_logic_vector(15 downto 0);
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signal inst_next, inst: std_logic_vector(15 downto 0);
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type regbank is array(0 to 15) of std_logic_vector(15 downto 0);
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signal reg_d: regbank;
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@ -62,7 +62,6 @@ begin
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load_reg_r: reg port map(clk => clk, rst => rst, d => load_reg_next, q => load_reg);
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load_addr_r: reg port map(clk => clk, rst => rst, d => load_addr_next, q => load_addr);
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hold_inst_r: reg port map(clk => clk, rst => rst, d => hold_inst_next, q => hold_inst);
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allregs:
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for i in 0 to 15 generate
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@ -73,15 +72,16 @@ begin
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begin
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if rst = '1' then
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cpu_state <= BRANCH; -- wait a cycle at first
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inst <= x"0000";
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elsif rising_edge(clk) then
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cpu_state <= cpu_state_next;
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inst <= inst_next;
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end if;
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end process;
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code_addr <= reg_q(14);
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process(code_data, reg_q, mem_in, mem_busy, alu_q, alu_flag, cpu_state, load_addr, load_reg, hold_inst) is
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variable inst: std_logic_vector(15 downto 0);
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process(code_data, reg_q, mem_in, mem_busy, alu_q, alu_flag, cpu_state, load_addr, load_reg, inst) is
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variable regn_0: natural;
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variable regn_1: natural;
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variable regn_2: natural;
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@ -110,9 +110,9 @@ begin
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case cpu_state is
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when RUN =>
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reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
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inst := code_data;
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inst_next <= code_data;
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when LOAD =>
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inst := x"0000"; -- NOP
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inst_next <= inst;
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mem_addr <= load_addr; -- maintain this until we're done reading
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if load_reg(3 downto 0) = x"e" then
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cpu_state_next <= BRANCH;
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@ -127,16 +127,18 @@ begin
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reg_d(regn_0) <= mem_in;
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end if;
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when BRANCH =>
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inst := x"0000"; -- NOP
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inst_next <= x"0000"; -- NOP
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reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
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when WAIT_MEM =>
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cpu_state_next <= RUN;
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inst := hold_inst;
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inst_next <= inst;
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reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
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if mem_busy = '1' then
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reg_d(14) <= reg_q(14); -- halt the prefetcher
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cpu_state_next <= WAIT_MEM;
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end if;
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end case;
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hold_inst_next <= inst;
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if cpu_state = RUN then
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regn_0 := to_integer(unsigned(inst(11 downto 8)));
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regn_1 := to_integer(unsigned(inst(7 downto 4)));
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regn_2 := to_integer(unsigned(inst(3 downto 0)));
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@ -146,11 +148,13 @@ begin
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when "0001" => -- LOAD rn, [rm, imm] (imm is signed 4 bits)
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if mem_busy = '1' then
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reg_d(14) <= reg_q(14); -- halt the prefetcher
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inst_next <= inst;
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cpu_state_next <= WAIT_MEM;
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else
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mem_read <= '1';
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cpu_state_next <= LOAD;
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reg_d(14) <= reg_q(14); -- halt the prefetcher
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-- inst_next <= inst;
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load_addr_next <= std_logic_vector(signed(reg_q(regn_1)) + signed(inst(3 downto 0) & '0'));
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mem_addr <= std_logic_vector(signed(reg_q(regn_1)) + signed(inst(3 downto 0) & '0'));
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@ -160,6 +164,7 @@ begin
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when "0010" => -- STORE rn, [rm, imm]
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if mem_busy = '1' then
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reg_d(14) <= reg_q(14); -- halt the prefetcher
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inst_next <= inst;
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cpu_state_next <= WAIT_MEM;
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else
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mem_write <= '1';
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@ -216,6 +221,7 @@ begin
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cpu_state_next <= BRANCH;
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end if;
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end if;
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end if;
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end process;
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end behavior;
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@ -92,7 +92,7 @@ def generate_ops(ops, labels, relocs):
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if isinstance(p, str): # label ref
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if len(params) == 1: # branch
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yield 14 # pc
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yield labels[p] - pc - 2
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yield labels[p] - pc - 4
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else: # set, allow relocs here
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relocs.append((pc, p))
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yield 0xff
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15
tools/cc.py
15
tools/cc.py
@ -473,10 +473,10 @@ class ShlOp(BinOp):
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return [f'set {sc1}, 1',
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f'or {self.dest}, {self.left}, {self.left}',
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f'sub {sc0}, {self.right}, {sc1}',
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f'beq [pc, 6]',
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f'beq [pc, 4]',
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f'add {self.dest}, {self.dest}, {self.dest}',
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f'sub {sc0}, {sc0}, {sc1}',
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f'bneq [pc, -6]']
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f'bneq [pc, -8]']
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class LtOp(BinOp):
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@ -485,7 +485,7 @@ class LtOp(BinOp):
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sc0 = scratches[0]
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return [f'set {self.dest}, 0',
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f'sub {sc0}, {self.left}, {self.right}',
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f'bneq [pc, 2]',
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f'bneq [pc, 0]',
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f'set {self.dest}, 1']
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class GtOp(LtOp):
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@ -531,7 +531,7 @@ class BoolNot(UnOp):
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def synth(self, scratches):
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return [f'set {self.dest}, 0',
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f'cmp {self.dest}, {self.operand}',
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f'bneq [pc, 2]',
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f'bneq [pc, 0]',
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f'set {self.dest}, 1']
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class NeqOp(BinOp):
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@ -555,7 +555,7 @@ class FnCall(AsmOp):
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sc0 = scratches[0]
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fn = self.dest_fn
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return out + [f'set {sc0}, 2',
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return out + [f'set {sc0}, 0',
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f'add lr, pc, {sc0}',
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f'or pc, {fn}, {fn}']
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@ -1375,10 +1375,11 @@ preamble = [f'_start:',
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f'set sp, 0',
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f'seth sp, {0x11}', # 256 bytes of stack ought to be enough
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f'set r2, main',
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f'set r3, 2',
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f'set r3, 0',
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f'add lr, pc, r3',
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f'or pc, r2, r2',
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f'or pc, pc, pc // loop forever',
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f'cmp r0, r0',
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f'beq [pc, -4] // loop forever',
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]
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def filter_dupes(ops):
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