cpu: more instruction pipelining

This is needed to make WNS room for fetching instructions from SRAM.
2021-04-17 23:02:58 -07:00
parent 6825ce464f
commit 36bc1417b6
3 changed files with 99 additions and 92 deletions
--- a/tools/as.py
+++ b/tools/as.py
@@ -92,7 +92,7 @@ def generate_ops(ops, labels, relocs):
            if isinstance(p, str):  # label ref
                if len(params) == 1:  # branch
                    yield 14 # pc
-                    yield labels[p] - pc - 2
+                    yield labels[p] - pc - 4
                else:  # set, allow relocs here
                    relocs.append((pc, p))
                    yield 0xff