cpu: more instruction pipelining

This is needed to make WNS room for fetching instructions from SRAM.
This commit is contained in:
Paul Mathieu
2021-04-17 23:02:58 -07:00
parent 6825ce464f
commit 36bc1417b6
3 changed files with 99 additions and 92 deletions

View File

@@ -92,7 +92,7 @@ def generate_ops(ops, labels, relocs):
if isinstance(p, str): # label ref
if len(params) == 1: # branch
yield 14 # pc
yield labels[p] - pc - 2
yield labels[p] - pc - 4
else: # set, allow relocs here
relocs.append((pc, p))
yield 0xff

View File

@@ -473,10 +473,10 @@ class ShlOp(BinOp):
return [f'set {sc1}, 1',
f'or {self.dest}, {self.left}, {self.left}',
f'sub {sc0}, {self.right}, {sc1}',
f'beq [pc, 6]',
f'beq [pc, 4]',
f'add {self.dest}, {self.dest}, {self.dest}',
f'sub {sc0}, {sc0}, {sc1}',
f'bneq [pc, -6]']
f'bneq [pc, -8]']
class LtOp(BinOp):
@@ -485,7 +485,7 @@ class LtOp(BinOp):
sc0 = scratches[0]
return [f'set {self.dest}, 0',
f'sub {sc0}, {self.left}, {self.right}',
f'bneq [pc, 2]',
f'bneq [pc, 0]',
f'set {self.dest}, 1']
class GtOp(LtOp):
@@ -531,7 +531,7 @@ class BoolNot(UnOp):
def synth(self, scratches):
return [f'set {self.dest}, 0',
f'cmp {self.dest}, {self.operand}',
f'bneq [pc, 2]',
f'bneq [pc, 0]',
f'set {self.dest}, 1']
class NeqOp(BinOp):
@@ -555,7 +555,7 @@ class FnCall(AsmOp):
sc0 = scratches[0]
fn = self.dest_fn
return out + [f'set {sc0}, 2',
return out + [f'set {sc0}, 0',
f'add lr, pc, {sc0}',
f'or pc, {fn}, {fn}']
@@ -1375,10 +1375,11 @@ preamble = [f'_start:',
f'set sp, 0',
f'seth sp, {0x11}', # 256 bytes of stack ought to be enough
f'set r2, main',
f'set r3, 2',
f'set r3, 0',
f'add lr, pc, r3',
f'or pc, r2, r2',
f'or pc, pc, pc // loop forever',
f'cmp r0, r0',
f'beq [pc, -4] // loop forever',
]
def filter_dupes(ops):