Initial commit
This commit is contained in:
Paul Mathieu
246
uart/uart.vhdl
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246
uart/uart.vhdl
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity uart is
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- hardware
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rx_pin : in std_logic;
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tx_pin : out std_logic;
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-- bus interface
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we : in std_logic;
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re : in std_logic;
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addr : in std_logic_vector(15 downto 0);
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din : in std_logic_vector(15 downto 0);
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dout : out std_logic_vector(15 downto 0)
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);
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end uart;
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--
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-- Mem layout:
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-- 0x00: 8-bit read/write
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-- 0x02: flags: [rxne, txe]
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-- Rx FIFO 4 bytes long
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-- Tx FIFO 4 bytes long
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-- Mnemonic: receive from the left, transmit to the right
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architecture Behavioral of uart is
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constant BAUD: positive := 115_200;
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constant SYSFREQ: natural := 100_000_000;
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constant CLKCNT: natural := SYSFREQ / BAUD;
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type Fifo is array(integer range <>) of std_logic_vector(7 downto 0);
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---- all dffs below
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signal rxfifo : Fifo(0 to 3);
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signal txfifo : Fifo(3 downto 0);
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signal rxcnt : unsigned(2 downto 0);
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signal txcnt : unsigned(2 downto 0);
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signal sysclk : unsigned(9 downto 0); -- up to 868 counts
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signal uarten : std_logic; -- 1 when state machines can do stuff
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type RxState_t is (IDLE, SHIFT_IN);
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type TxState_t is (IDLE, SHIFT_OUT);
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signal rxstate: RxState_t;
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signal txstate: TxState_t;
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signal txpopped : std_logic;
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signal rxpushed : std_logic;
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signal txshift : std_logic_vector(7 downto 0);
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signal rxshift : std_logic_vector(7 downto 0);
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signal txshiftcnt : unsigned(3 downto 0);
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signal rxshiftcnt : unsigned(3 downto 0);
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begin
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-- rx process
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-- drives rxstate, rxpushed, rxshift, rxshiftcnt, rxfifo
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process(clk, rst)
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begin
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if rst = '1' then
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rxstate <= IDLE;
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rxpushed <= '0';
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rxshift <= x"00";
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rxshiftcnt <= "0000";
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for i in 0 to 3 loop
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rxfifo(i) <= x"00";
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end loop;
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elsif rising_edge(clk) and uarten = '1' then
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rxpushed <= '0';
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case rxstate is
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when IDLE =>
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if rx_pin = '0' then -- start bit!! (hopefully)
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rxshift <= x"00";
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rxshiftcnt <= "0000";
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rxstate <= SHIFT_IN;
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end if;
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when SHIFT_IN =>
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if rxshiftcnt = 8 then
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-- by now we should be seeing the stop bit, check
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if rx_pin = '1' then -- all good, push away
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for i in 2 downto 0 loop -- right to left
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rxfifo(i + 1) <= rxfifo(i);
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end loop;
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rxfifo(0) <= rxshift;
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rxpushed <= '1';
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end if;
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rxstate <= IDLE; -- either way, we're done
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else
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rxshift <= rx_pin & rxshift(7 downto 1);
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rxshiftcnt <= rxshiftcnt + 1;
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end if;
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end case;
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end if;
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end process;
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-- tx process
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-- drives txstate, txpopped, txshift, txshiftcnt, tx_pin
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process(clk, rst)
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begin
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if rst = '1' then
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txstate <= IDLE;
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txpopped <= '0';
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txshift <= x"00";
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txshiftcnt <= "0000";
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tx_pin <= '1';
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elsif rising_edge(clk) and uarten = '1' then
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txpopped <= '0';
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case txstate is
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when IDLE =>
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if txcnt > 0 then
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txshiftcnt <= "0000";
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tx_pin <= '0'; -- start bit
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txstate <= SHIFT_OUT;
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txshift <= txfifo(0);
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txpopped <= '1';
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else
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tx_pin <= '1';
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end if;
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when SHIFT_OUT =>
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if txshiftcnt = 8 then
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tx_pin <= '1';
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txstate <= IDLE;
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else
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txshiftcnt <= txshiftcnt + 1;
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tx_pin <= txshift(0);
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txshift(6 downto 0) <= txshift(7 downto 1);
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end if;
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end case;
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end if;
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end process;
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process(clk, rst) -- drives sysclk, uarten
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begin
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if rst = '1' then
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sysclk <= to_unsigned(0, 10);
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uarten <= '0';
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elsif rising_edge(clk) then
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if sysclk = to_unsigned(CLKCNT - 1, 10) then
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sysclk <= to_unsigned(0, 10);
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uarten <= '1';
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else
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sysclk <= sysclk + 1;
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uarten <= '0';
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end if;
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end if;
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end process;
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process(clk, rst) -- drives dout, rxcnt, txcnt, txfifo
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variable txn: unsigned(2 downto 0);
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variable rxn: unsigned(2 downto 0);
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variable txpopdone : std_logic := '0'; -- latch
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variable rxpushdone : std_logic := '0'; -- latch
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begin
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rxn := rxcnt;
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txn := txcnt;
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if rst = '1' then
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for i in 0 to 3 loop
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txfifo(i) <= x"00";
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end loop;
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rxcnt <= "000";
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txcnt <= "000";
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txpopdone := '0';
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rxpushdone := '0';
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elsif rising_edge(clk) then
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dout <= x"0000";
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-- Fifo grooming
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if txpopped = '1' then
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if txpopdone = '0' then
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-- shift our fifo to the right
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for i in 0 to 2 loop -- 0 to 2 is right to left
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txfifo(i) <= txfifo(i + 1);
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end loop;
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txpopdone := '1';
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txn := txcnt - 1;
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end if;
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else
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txpopdone := '0';
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end if;
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if rxpushed = '1' then
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if rxpushdone = '0' then
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-- our fifo was already moved, just update rxn
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if rxcnt < 4 then
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rxn := rxcnt + 1;
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end if;
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rxpushdone := '1';
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end if;
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else
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rxpushdone := '0';
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end if;
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txcnt <= txn;
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rxcnt <= rxn;
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-- logic here
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case addr is
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when x"0000" =>
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if we = '1' then
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if to_integer(txn) < 4 then
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txfifo(to_integer(txn)) <= din(7 downto 0);
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txcnt <= txn + 1;
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end if;
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elsif re = '1' then
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if to_integer(rxn) > 0 then
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dout(7 downto 0) <= rxfifo(to_integer(rxn) - 1);
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rxcnt <= rxn - 1;
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end if;
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end if;
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when x"0002" =>
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if to_integer(rxn) > 0 then
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dout(1) <= '1';
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else
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dout(1) <= '0';
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end if;
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if to_integer(txn) = 0 then
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dout(0) <= '1';
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else
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dout(0) <= '0';
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end if;
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when others =>
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-- nada
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end case;
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end if;
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end process;
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end Behavioral;
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