Initial commit

first/rom.vhdl

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Aligned IO only.
+-- Unaligned address bits are ignored.
+-- E.g. on a 16-bit bus, last address bit is ignored.
+entity rom is
+  generic
+  (
+    addressWidth : in positive := 16;
+    busWidth : in positive := 16
+  );
+  port
+  (
+    address : in unsigned(addressWidth - 1 downto 0);
+    dataOut : out std_logic_vector(busWidth - 1 downto 0)
+  );
+end rom;
+
+architecture Behavioral of rom is
+  constant alignment : positive := busWidth / 8;
+
+  type romtype is array(0 to 2) of std_logic_vector(15 downto 0);
+  signal romdata: romtype := (
+        x"0002",
+        x"0004",
+        x"0000"
+  );
+begin
+
+  process(address) is
+    variable index: natural;
+  begin
+    index := to_integer(unsigned(address)) / alignment;
+    dataOut <= romdata(index);
+  end process;
+
+end Behavioral;