Initial commit

first/ram.vhdl

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Aligned IO only.
+-- Unaligned address bits are ignored.
+-- E.g. on a 16-bit bus, last address bit is ignored.
+entity ram is
+  generic
+  (
+    addressWidth : in positive := 16;
+    busWidth : in positive := 16;
+    size : in positive := 1024
+  );
+  port
+  (
+    clk : in std_logic;
+    address : in std_logic_vector(addressWidth - 1 downto 0);
+    writeEnable : in std_logic;
+    dataIn : in std_logic_vector(busWidth - 1 downto 0);
+    dataOut : out std_logic_vector(busWidth - 1 downto 0)
+  );
+end ram;
+
+architecture Behavioral of ram is
+  constant alignment : positive := busWidth / 8;
+  constant ramSize : positive := size / alignment;
+
+  type ramType is array(natural range <>) of std_logic_vector(busWidth - 1 downto 0);
+  subtype ramRange is natural range 0 to ramSize;
+
+  signal mem : ramType(ramRange);
+begin
+  process(clk)
+    variable index : ramRange;
+  begin
+    if (rising_edge(clk))
+    then
+      index := to_integer(unsigned(address)) / alignment;
+
+      if (writeEnable = '1')
+      then
+        mem(index) <= dataIn;
+      end if;
+
+      dataOut <= mem(index);
+    end if;
+  end process;
+end Behavioral;