Initial commit

first/or.vhdl

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+-- Simple OR gate design
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity or_gate is
+port(
+  a: in std_logic;
+  b: in std_logic;
+  q: out std_logic);
+end or_gate;
+
+architecture rtl of or_gate is
+begin
+  q <= a or b;
+end rtl;