pol/synth
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

wave: fix write to busy sysbus

Browse Source
This commit is contained in:
Paul Mathieu 2021-04-24 08:55:23 -07:00
parent c12c28fb44
commit 3294e7082b
2 changed files with 28 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
wave/square.vhdl
View File

@ -85,7 +85,7 @@ begin
if enabled = '1' then if enabled = '1' then
if active = '1' and m_busy = '1' then if active = '1' and m_busy = '1' then
deferred := '1'; deferred := '1';
elsif deferred = '1' or (active = '1' and m_busy = '0') then elsif m_busy = '0' and (deferred = '1' or active = '1') then
m_we <= '1'; m_we <= '1';
m_addr <= out_addr; m_addr <= out_addr;
if high = '1' then if high = '1' then

34
wave/square_test.vhdl
View File

@ -32,6 +32,9 @@ architecture rtl of square_test is
signal s_we, m_busy, m_we: std_logic; signal s_we, m_busy, m_we: std_logic;
signal s_addr, s_din, m_addr, m_dout: std_logic_vector(15 downto 0); signal s_addr, s_din, m_addr, m_dout: std_logic_vector(15 downto 0);
constant period: integer := 7;
constant half_time: time := 1280 ns * period;
begin begin
dut: square port map(clk => clk, rst => rst, dut: square port map(clk => clk, rst => rst,
s_we => s_we, s_addr => s_addr, s_din => s_din, s_we => s_we, s_addr => s_addr, s_din => s_din,
@ -63,7 +66,7 @@ begin
s_we <= '1'; s_we <= '1';
s_addr <= x"0000"; -- period s_addr <= x"0000"; -- period
s_din <= x"0001"; -- 256 cycles (2560 ns) s_din <= std_logic_vector(to_unsigned(period, 16));
wait for 10 ns; wait for 10 ns;
@ -80,7 +83,7 @@ begin
wait for 10 ns; wait for 10 ns;
s_we <= '1'; s_we <= '1';
s_addr <= x"0006"; -- DNA address s_addr <= x"0006"; -- DMA address
s_din <= x"babe"; s_din <= x"babe";
wait for 10 ns; wait for 10 ns;
@ -91,18 +94,35 @@ begin
wait for 20 ns; wait for 20 ns;
assert(m_addr = x"babe") report "Fail to write to mem addr" severity error; -- assert(m_addr = x"babe") report "Fail to write to mem addr" severity error;
assert(m_we = '1') report "Fail to write to mem we" severity error; -- assert(m_we = '1') report "Fail to write to mem we" severity error;
assert(m_dout = x"0037") report "Fail to write to mem dout" severity error; -- assert(m_dout = x"0037") report "Fail to write to mem dout" severity error;
wait for 20 ns; wait for 20 ns;
assert(m_we = '0') report "Fail to stop m_we" severity error; -- assert(m_we = '0') report "Fail to stop m_we" severity error;
wait for 1300 ns; wait for half_time;
assert(m_dout = x"0037") report "Fail to write to mem dout" severity error;
m_busy <= '1';
wait for half_time;
assert(m_we = '0') report "Blarg" severity error;
assert(m_dout = x"0037") report "Fail to write to mem dout" severity error;
m_busy <= '0';
wait for 10 ns;
assert(m_we = '1') report "Blarg" severity error;
assert(m_dout = x"0042") report "Fail to write to mem dout" severity error; assert(m_dout = x"0042") report "Fail to write to mem dout" severity error;
wait for 100 us;
assert false report "Test done." severity note; assert false report "Test done." severity note;
finished <= '1'; finished <= '1';