wave: fix write to busy sysbus

2021-04-24 08:55:23 -07:00
parent c12c28fb44
commit 3294e7082b
2 changed files with 28 additions and 8 deletions
--- a/wave/square.vhdl
+++ b/wave/square.vhdl
@@ -85,7 +85,7 @@ begin
      if enabled = '1' then
        if active = '1' and m_busy = '1' then
          deferred := '1';
-        elsif deferred = '1' or (active = '1' and m_busy = '0') then
+        elsif m_busy = '0' and (deferred = '1' or active = '1') then
          m_we <= '1';
          m_addr <= out_addr;
          if high = '1' then