dsp: update test
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5948622212
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@ -32,8 +32,10 @@ architecture rtl of dsp_test is
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signal led: std_logic_vector(7 downto 0);
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signal led: std_logic_vector(7 downto 0);
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signal uart_rx: std_logic;
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signal uart0_rx: std_logic;
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signal uart_tx: std_logic;
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signal uart0_tx: std_logic;
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signal uart1_rx: std_logic;
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signal uart1_tx: std_logic;
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signal pdmout0: std_logic;
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signal pdmout0: std_logic;
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type str is array(integer range <>) of std_logic_vector(7 downto 0);
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type str is array(integer range <>) of std_logic_vector(7 downto 0);
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@ -65,7 +67,8 @@ architecture rtl of dsp_test is
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begin
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begin
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dut: dsp port map(clk => clk, rst => rst,
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dut: dsp port map(clk => clk, rst => rst,
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led => led, uart_rx => uart_rx, uart_tx => uart_tx,
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led => led, uart0_rx => uart0_rx, uart0_tx => uart0_tx,
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uart1_rx => uart1_rx, uart1_tx => uart1_tx,
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pdmout0_pin => pdmout0);
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pdmout0_pin => pdmout0);
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@ -75,22 +78,24 @@ begin
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begin
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begin
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rst <= '1';
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rst <= '1';
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uart_rx <= '1';
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uart0_rx <= '1';
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wait for 15 ns;
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wait for 15 ns;
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assert(led=x"00") report "Fail rst" severity error;
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assert(led=x"00") report "Fail rst" severity error;
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rst <= '0';
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rst <= '0';
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-- wait for 20 us;
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wait for 20 us;
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-- uart_send(prog, uart_rx);
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uart_send(prog, uart0_rx);
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wait for 2 us;
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assert(led = x"f0") report "Fail prog" severity error;
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-- uart_send(jump, uart0_rx);
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-- wait for 2 us;
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-- wait for 2 us;
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-- assert(led = x"f0") report "Fail prog" severity error;
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-- assert(led = x"2a") report "Fail prog" severity error;
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-- uart_send(jump, uart_rx);
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-- wait for 2 us;
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-- assert(led = x"01") report "Fail prog" severity error;
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wait for 200 us;
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-- wait for 200 us;
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-- uart_send(midi, uart1_rx);
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assert false report "Test done." severity note;
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assert false report "Test done." severity note;
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