cpu: wait when mem_busy is high

cpu/cpu_test.vhdl

@@ -19,7 +19,8 @@ architecture rtl of cpu_test is
                          mem_out: out std_logic_vector(15 downto 0);
                          mem_addr: out std_logic_vector(15 downto 0);
                          mem_write: out std_logic;
-                         mem_read: out std_logic
+                         mem_read: out std_logic;
+                         mem_busy: in std_logic
                        );
   end component;
 
@@ -40,14 +41,14 @@ architecture rtl of cpu_test is
   );
 
   signal finished, clk, rst: std_logic := '0';
-  signal mem_write, mem_read: std_logic;
+  signal mem_write, mem_read, mem_busy: std_logic;
   signal rom_data, rom_addr, mem_in, mem_out, mem_addr: std_logic_vector(15 downto 0);
 
 begin
   dut: cpu port map(clk => clk, rst => rst,
                     code_data => rom_data, code_addr => rom_addr,
                     mem_in => mem_in, mem_out => mem_out, mem_addr => mem_addr,
-                    mem_write => mem_write, mem_read => mem_read);
+                    mem_write => mem_write, mem_read => mem_read, mem_busy => mem_busy);
 
   -- clock
   process
@@ -97,6 +98,14 @@ begin
     assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
     assert(mem_out=x"002a") report "Fail set mem_out to 42" severity error;
 
+    mem_busy <= '1';
+
+    wait for 10 ns;
+    assert(rom_addr=x"0008") report "Fail hold PC @08" severity error;
+    assert(mem_read='0') report "Fail to wait until mem_busy is low" severity error;
+
+    mem_busy <= '0';
+
     wait for 10 ns;
     assert(rom_addr=x"000a") report "Fail PC @08" severity error;
     assert(mem_write='0') report "Fail set mem_write to 0" severity error;