Add dsp
With: - LED control - UART - PDM out - square wave generator (DMA to PDM out (was it really necessary?)) - sample program that plays a square wave from UART values
This commit is contained in:
Paul Mathieu
parent
75b5488b8d
commit
14dba00fd0
49
dsp/boot_rom.vhdl.in
Normal file
49
dsp/boot_rom.vhdl.in
Normal file
@ -0,0 +1,49 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity boot_rom is
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generic
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(
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addressWidth : in positive := 16;
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busWidth : in positive := 16
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);
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port
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(
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clk: in std_logic;
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code_addr : in std_logic_vector(15 downto 0);
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code_out : out std_logic_vector(15 downto 0);
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data_addr : in std_logic_vector(15 downto 0);
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data_out : out std_logic_vector(15 downto 0)
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);
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end boot_rom;
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architecture Behavioral of boot_rom is
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constant alignment: positive := busWidth / 8;
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constant romsize: natural := $nwords;
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type romtype is array(0 to romsize - 1) of std_logic_vector(15 downto 0);
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signal romdata: romtype := (
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$words
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);
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begin
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process(clk) is
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variable code_index: natural;
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variable data_index: natural;
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begin
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if rising_edge(clk) then
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code_index := to_integer(unsigned(code_addr)) / alignment;
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if code_index < romsize then
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code_out <= romdata(code_index);
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else
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code_out <= x"0000";
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end if;
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data_index := to_integer(unsigned(data_addr)) / alignment;
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data_out <= romdata(data_index);
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end if;
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end process;
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end Behavioral;
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287
dsp/dsp.vhdl
Normal file
287
dsp/dsp.vhdl
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@ -0,0 +1,287 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity dsp is
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port
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(
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clk: in std_logic;
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rst: in std_logic;
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led: out std_logic_vector(7 downto 0);
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uart_rx: in std_logic;
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uart_tx: out std_logic;
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pdmout0_pin: out std_logic
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);
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end dsp;
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architecture rtl of dsp is
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component cpu is port
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(
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clk: in std_logic;
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rst: in std_logic;
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code_data: in std_logic_vector(15 downto 0);
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code_addr: out std_logic_vector(15 downto 0);
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mem_in: in std_logic_vector(15 downto 0);
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mem_out: out std_logic_vector(15 downto 0);
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mem_addr: out std_logic_vector(15 downto 0);
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mem_write: out std_logic;
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mem_read: out std_logic;
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mem_busy: in std_logic
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);
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end component;
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component ram is
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generic
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(
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addressWidth : in positive := 16;
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busWidth : in positive := 16;
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size : in positive := 1024
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);
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port
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(
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clk : in std_logic;
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address : in std_logic_vector(addressWidth - 1 downto 0);
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writeEnable : in std_logic;
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dataIn : in std_logic_vector(busWidth - 1 downto 0);
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dataOut : out std_logic_vector(busWidth - 1 downto 0)
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);
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end component;
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component boot_rom is port
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(
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clk: in std_logic;
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code_addr : in std_logic_vector(15 downto 0);
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code_out : out std_logic_vector(15 downto 0);
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data_addr : in std_logic_vector(15 downto 0);
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data_out : out std_logic_vector(15 downto 0)
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);
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end component;
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component uart is
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- hardware
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rx_pin : in std_logic;
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tx_pin : out std_logic;
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-- bus interface
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we : in std_logic;
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re : in std_logic;
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addr : in std_logic_vector(15 downto 0);
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din : in std_logic_vector(15 downto 0);
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dout : out std_logic_vector(15 downto 0)
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);
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end component;
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component sysbus is
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port
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(
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clk: in std_logic;
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rst: in std_logic;
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-- master port 0
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m0_addr: in std_logic_vector(15 downto 0);
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m0_wdata: in std_logic_vector(15 downto 0);
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m0_rdata: out std_logic_vector(15 downto 0);
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m0_re: in std_logic;
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m0_we: in std_logic;
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m0_busy: out std_logic;
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-- master port 1
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m1_addr: in std_logic_vector(15 downto 0);
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m1_wdata: in std_logic_vector(15 downto 0);
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m1_rdata: out std_logic_vector(15 downto 0);
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m1_re: in std_logic;
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m1_we: in std_logic;
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m1_busy: out std_logic;
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-- actual bus
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bus_addr: out std_logic_vector(15 downto 0);
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bus_wdata: out std_logic_vector(15 downto 0);
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bus_rdata: in std_logic_vector(15 downto 0);
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bus_re: out std_logic;
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bus_we: out std_logic
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);
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end component;
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component pdmout is
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- hardware
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out_pin : out std_logic;
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-- bus interface
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we : in std_logic;
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addr : in std_logic_vector(15 downto 0);
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din : in std_logic_vector(15 downto 0)
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);
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end component;
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component square is
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- bus slave interface
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s_we : in std_logic;
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s_addr : in std_logic_vector(15 downto 0);
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s_din : in std_logic_vector(15 downto 0);
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-- bus master interface (DMA!!)
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m_busy : in std_logic;
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m_we : out std_logic;
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m_addr : out std_logic_vector(15 downto 0);
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m_dout : out std_logic_vector(15 downto 0)
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);
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end component;
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signal mem_write : std_logic;
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signal rom_code_addr, rom_code_out, mem_in, mem_out, mem_addr: std_logic_vector(15 downto 0);
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signal rom_data_addr, rom_data_out: std_logic_vector(15 downto 0);
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signal uart_din, uart_dout, uart_addr: std_logic_vector(15 downto 0);
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signal uart_we, uart_re: std_logic;
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signal cpu_write, cpu_read, cpu_busy: std_logic;
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signal cpu_mosi, cpu_miso, cpu_addr: std_logic_vector(15 downto 0);
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signal square_write, square_busy: std_logic;
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signal square_mosi, square_addr: std_logic_vector(15 downto 0);
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signal square0_s_din, square0_s_addr: std_logic_vector(15 downto 0);
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signal square0_s_we : std_logic;
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signal pdmout0_din, pdmout0_addr: std_logic_vector(15 downto 0);
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signal pdmout0_we : std_logic;
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signal bus_write, bus_read: std_logic;
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signal bus_mosi, bus_miso, bus_addr: std_logic_vector(15 downto 0);
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signal led_r, led_next: std_logic_vector(7 downto 0);
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begin
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cpu0: cpu port map(clk => clk, rst => rst,
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code_data => rom_code_out, code_addr => rom_code_addr,
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mem_in => cpu_miso, mem_out => cpu_mosi, mem_addr => cpu_addr,
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mem_write => cpu_write, mem_read => cpu_read, mem_busy => cpu_busy);
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rom: boot_rom port map(clk => clk, code_addr => rom_code_addr, code_out => rom_code_out,
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data_addr => rom_data_addr, data_out => rom_data_out);
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mem: ram port map(clk => clk, address => mem_addr, writeEnable => mem_write,
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dataIn => mem_in, dataOut => mem_out);
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uart0: uart port map(clk => clk, rst => rst, rx_pin => uart_rx, tx_pin => uart_tx,
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addr => uart_addr, din => uart_din, dout => uart_dout,
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re => uart_re, we => uart_we);
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square0: square port map(clk => clk, rst => rst,
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s_we => square0_s_we, s_addr => square0_s_addr, s_din => square0_s_din,
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m_busy => square_busy, m_we => square_write,
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m_addr => square_addr, m_dout => square_mosi);
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pdmout0: pdmout port map(clk => clk, rst => rst,
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out_pin => pdmout0_pin,
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we => pdmout0_we, addr => pdmout0_addr, din => pdmout0_din);
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main_bus: sysbus port map(clk => clk, rst => rst,
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m0_addr => cpu_addr, m0_wdata => cpu_mosi, m0_rdata => cpu_miso,
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m0_re => cpu_read, m0_we => cpu_write, m0_busy => cpu_busy,
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m1_addr => square_addr, m1_wdata => square_mosi, m1_rdata => open,
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m1_re => '0', m1_we => square_write, m1_busy => square_busy,
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bus_addr => bus_addr, bus_wdata => bus_mosi, bus_rdata => bus_miso,
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bus_re => bus_read, bus_we => bus_write
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);
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-- system map
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-- 0x0000 - 0x0fff ROM
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-- 0x1000 - 0x1fff RAM
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-- 0xc000 - 0xc00f LED0
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-- 0xc010 - 0xc01f UART0
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-- 0xc020 - 0xc02f PDMOUT0
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-- 0xc030 - 0xc03f SQUARE0
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led <= led_r;
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process(clk, rst)
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begin
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if rising_edge(clk) then
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led_r <= led_next;
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end if;
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if rst = '1' then
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led_r <= x"00";
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end if;
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end process;
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process(bus_addr, bus_mosi, bus_write, mem_out, rst, rom_data_out, led_r, bus_read)
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begin
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bus_miso <= x"0000";
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rom_data_addr <= bus_addr and x"0fff";
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mem_addr <= bus_addr and x"0fff";
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mem_in <= bus_mosi;
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mem_write <= '0';
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led_next <= led_r;
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uart_din <= bus_mosi;
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uart_addr <= bus_addr and x"000f";
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uart_we <= '0';
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uart_re <= '0';
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pdmout0_we <= '0';
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pdmout0_addr <= bus_addr and x"000f";
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pdmout0_din <= bus_mosi;
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square0_s_we <= '0';
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square0_s_addr <= bus_addr and x"000f";
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square0_s_din <= bus_mosi;
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case bus_addr(15 downto 12) is
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when x"0" =>
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bus_miso <= rom_data_out;
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when x"1" =>
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bus_miso <= mem_out;
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mem_write <= bus_write;
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when x"c" =>
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case bus_addr(7 downto 4) is
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when x"0" => -- LED
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if bus_write = '1' then
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led_next <= bus_mosi(7 downto 0);
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end if;
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when x"1" => -- UART0
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bus_miso <= uart_dout;
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uart_we <= bus_write;
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uart_re <= bus_read;
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when x"2" => -- PDMOUT0
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pdmout0_we <= bus_write;
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when x"3" => -- SQUARE0
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square0_s_we <= bus_write;
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when others =>
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end case;
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when others =>
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end case;
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end process;
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end rtl;
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80
dsp/dsp_test.vhdl
Normal file
80
dsp/dsp_test.vhdl
Normal file
@ -0,0 +1,80 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity dsp_test is
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end dsp_test;
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architecture rtl of dsp_test is
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component clock is port(clk: out std_logic);
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end component;
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component dsp is
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port(
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clk: in std_logic;
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rst: in std_logic;
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led: out std_logic_vector(7 downto 0);
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uart_rx: in std_logic;
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uart_tx: out std_logic;
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pdmout0_pin: out std_logic
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);
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end component;
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signal finished, clk, rst: std_logic := '0';
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signal led: std_logic_vector(7 downto 0);
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signal uart_rx: std_logic;
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signal uart_tx: std_logic;
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signal pdmout0: std_logic;
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type str is array(integer range <>) of std_logic_vector(7 downto 0);
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signal blarg: str(0 to 4) := (x"61", x"64", x"64", x"61", x"64");
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begin
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dut: dsp port map(clk => clk, rst => rst,
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led => led, uart_rx => uart_rx, uart_tx => uart_tx,
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pdmout0_pin => pdmout0);
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clk <= not clk after 5 ns when finished /= '1' else '0';
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process
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begin
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rst <= '1';
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uart_rx <= '1';
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wait for 15 ns;
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assert(led=x"00") report "Fail rst" severity error;
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rst <= '0';
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wait for 20 us;
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for i in 0 to 4 loop
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uart_rx <= '0'; -- start bit
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wait for 8681 ns;
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for j in 0 to 7 loop
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uart_rx <= blarg(i)(j);
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wait for 8681 ns;
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end loop;
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uart_rx <= '1'; -- stop bit
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wait for 8681 ns;
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end loop;
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wait for 2 ms;
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assert false report "Test done." severity note;
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finished <= '1';
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wait;
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end process;
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end rtl;
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5
dsp/led.h
Normal file
5
dsp/led.h
Normal file
@ -0,0 +1,5 @@
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#pragma once
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struct led {
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volatile uint8_t output;
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};
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35
dsp/main.c
Normal file
35
dsp/main.c
Normal file
@ -0,0 +1,35 @@
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#include "sys.h"
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void init() {
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square0->output_address = pdmout0;
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square0->high_val = 0xffff;
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square0->low_val = 0x0000;
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square0->flags = SQUARE_FLAG_ENABLE_msk;
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// will set the period later
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}
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int main() {
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init();
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while(1) {
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uint8_t c = uart_read(uart0);
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uint16_t period;
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if (c == 'c') {
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period = 1493; // C4, 262.63 Hz, maybe
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} else if (c == 'd') {
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period = 1330; // D4, 293.66 Hz, maybe
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} else if (c == 'e') {
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period = 1185; // E4, 329.63 Hz, maybe
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} else if (c == 'f') {
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period = 1119; // F4, 249.23 Hz, maybe
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} else if (c == 'g') {
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period = 996; // G4, 392.00 Hz, maybe
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} else if (c == 'a') {
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period = 887; // A4, 440.00 Hz, maybe
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} else if (c == 'b') {
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period = 791; // B4, 493.88 Hz, maybe
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}
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square0->period = period;
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}
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}
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39
dsp/makefile
Normal file
39
dsp/makefile
Normal file
@ -0,0 +1,39 @@
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all: sim rom
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sim: dsp_test.ghw
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rom: boot_rom.gen.vhdl
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CC = ../bin/cc
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LD = ../bin/ld
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CFLAGS = -I../wave -I../uart
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boot_rom.gen.vhdl: main.o ../uart/uart.o
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sim_sources = dsp_test.vhdl
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sources = boot_rom.gen.vhdl dsp.vhdl \
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../cpu/cpu.vhdl ../cpu/reg.vhdl \
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$(wildcard ../wave/*.vhdl) \
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$(wildcard ../sysbus/*.vhdl) \
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../uart/uart.vhdl \
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../first/ram.vhdl
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%.gen.vhdl:
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$(LD) -o $@ --vhdl $*.vhdl.in $^
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|
||||
|
||||
%.ghw: work-obj93.cf
|
||||
ghdl -r $* --wave=$@ --assert-level=error
|
||||
|
||||
|
||||
work-obj93.cf: $(sim_sources) $(sources)
|
||||
ghdl -a $^
|
||||
|
||||
PHONY: sim clean
|
||||
|
||||
clean:
|
||||
rm -rf *.o *.gen.vhdl *.ghw work-obj93.cf
|
||||
|
||||
.DELETE_ON_ERROR:
|
||||
|
||||
.PRECIOUS: %.ghw
|
||||
15
dsp/sys.h
Normal file
15
dsp/sys.h
Normal file
@ -0,0 +1,15 @@
|
||||
#pragma once
|
||||
|
||||
#include "led.h"
|
||||
#include "uart.h"
|
||||
#include "wave.h"
|
||||
|
||||
#define LED0_BASE 0xc000
|
||||
#define UART0_BASE 0xc010
|
||||
#define PDMOUT0_BASE 0xc020
|
||||
#define SQUARE0_BASE 0xc030
|
||||
|
||||
#define led0 ((struct led*) LED0_BASE)
|
||||
#define uart0 ((struct uart*) UART0_BASE)
|
||||
#define pdmout0 ((struct pdmout*) PDMOUT0_BASE)
|
||||
#define square0 ((struct square*) SQUARE0_BASE)
|
||||
Loading…
Reference in New Issue
Block a user