Add dsp

With:
- LED control
- UART
- PDM out
- square wave generator (DMA to PDM out (was it really necessary?))
- sample program that plays a square wave from UART values

dsp/dsp_test.vhdl

@@ -0,0 +1,80 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+entity dsp_test is
+end dsp_test;
+
+architecture rtl of dsp_test is
+
+  component clock is port(clk: out std_logic);
+  end component;
+
+  component dsp is
+    port(
+          clk: in std_logic;
+          rst: in std_logic;
+
+          led: out std_logic_vector(7 downto 0);
+
+          uart_rx: in std_logic;
+          uart_tx: out std_logic;
+
+          pdmout0_pin: out std_logic
+        );
+  end component;
+
+  signal finished, clk, rst: std_logic := '0';
+
+  signal led: std_logic_vector(7 downto 0);
+
+  signal uart_rx: std_logic;
+  signal uart_tx: std_logic;
+  signal pdmout0: std_logic;
+
+  type str is array(integer range <>) of std_logic_vector(7 downto 0);
+  signal blarg: str(0 to 4) := (x"61", x"64", x"64", x"61", x"64");
+
+begin
+  dut: dsp port map(clk => clk, rst => rst,
+                    led => led, uart_rx => uart_rx, uart_tx => uart_tx,
+                    pdmout0_pin => pdmout0);
+
+
+  clk <= not clk after 5 ns when finished /= '1' else '0';
+
+  process
+  begin
+    rst <= '1';
+
+    uart_rx <= '1';
+
+    wait for 15 ns;
+    assert(led=x"00") report "Fail rst" severity error;
+
+    rst <= '0';
+
+    wait for 20 us;
+    for i in 0 to 4 loop
+      uart_rx <= '0';  -- start bit
+      wait for 8681 ns;
+
+      for j in 0 to 7 loop
+        uart_rx <= blarg(i)(j);
+        wait for 8681 ns;
+      end loop;
+
+      uart_rx <= '1';  -- stop bit
+      wait for 8681 ns;
+
+    end loop;
+
+    wait for 2 ms;
+
+    assert false report "Test done." severity note;
+
+    finished <= '1';
+    wait;
+  end process;
+end rtl;