uart: fix synthesis warnings

uart/uart.vhdl

@@ -32,7 +32,7 @@ end uart;
 -- Mnemonic: receive from the left, transmit to the right
 
 architecture Behavioral of uart is
-  constant BAUD: positive := 115_200;
+  constant BAUD: positive := 1_000_000;
   constant SYSFREQ: natural := 100_000_000;
   constant CLKCNT: natural := SYSFREQ / BAUD;
 
@@ -78,7 +78,8 @@ begin
       for i in 0 to 3 loop
         rxfifo(i) <= x"00";
       end loop;
-    elsif rising_edge(clk) and uarten = '1' then
+    elsif rising_edge(clk) then
+      if uarten = '1' then
         rxpushed <= '0';
 
         case rxstate is
@@ -105,6 +106,7 @@ begin
             end if;
         end case;
       end if;
+    end if;
   end process;
 
   -- tx process
@@ -117,7 +119,8 @@ begin
       txshift <= x"00";
       txshiftcnt <= "0000";
       tx_pin <= '1';
-    elsif rising_edge(clk) and uarten = '1' then
+    elsif rising_edge(clk) then
+      if uarten = '1' then
         txpopped <= '0';
 
         case txstate is
@@ -142,6 +145,7 @@ begin
             end if;
         end case;
       end if;
+    end if;
   end process;
 
   process(clk, rst)  -- drives sysclk, uarten
@@ -167,8 +171,6 @@ begin
     variable txpopdone  : std_logic := '0'; -- latch
     variable rxpushdone : std_logic := '0'; -- latch
   begin
-    rxn := rxcnt;
-    txn := txcnt;
 
     if rst = '1' then
       for i in 0 to 3 loop
@@ -181,6 +183,9 @@ begin
       txpopdone := '0';
       rxpushdone := '0';
     elsif rising_edge(clk) then
+      rxn := rxcnt;
+      txn := txcnt;
+
       dout <= x"0000";
 
       -- Fifo grooming