16 lines
227 B
VHDL
16 lines
227 B
VHDL
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-- Simple OR gate design
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity or_gate is
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port(
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a: in std_logic;
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b: in std_logic;
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q: out std_logic);
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end or_gate;
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architecture rtl of or_gate is
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begin
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q <= a or b;
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end rtl;
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