79 lines
1.5 KiB
VHDL
79 lines
1.5 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity pdmout is
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- hardware
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out_pin : out std_logic;
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-- bus interface
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we : in std_logic;
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addr : in std_logic_vector(15 downto 0);
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din : in std_logic_vector(15 downto 0)
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);
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end pdmout;
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--
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-- Mem layout:
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-- 0x00: 16-bit unsigned amplitude
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-- 0x02: flags: [enabled]
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architecture Behavioral of pdmout is
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signal sample: std_logic_vector(15 downto 0);
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signal feedback: signed(16 downto 0);
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signal enabled: std_logic;
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begin
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-- PDM process
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-- drives pin_out, feedback
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process(clk, rst)
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begin
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if rst = '1' then
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feedback <= to_signed(0, 17);
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out_pin <= '0';
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elsif rising_edge(clk) then
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if feedback > 0 then
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out_pin <= '1';
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feedback <= feedback + signed("0" & sample) - ("0" & x"ffff");
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else
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out_pin <= '0';
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feedback <= feedback + signed("0" & sample);
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end if;
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end if;
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end process;
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-- Bus process
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-- drives sample, enabled
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process(clk, rst)
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begin
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if rst = '1' then
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sample <= x"0000";
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enabled <= '0';
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elsif rising_edge(clk) then
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case addr(3 downto 0) is
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when x"0" =>
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if we = '1' then
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sample <= din;
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end if;
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when x"2" =>
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if we = '1' then
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enabled <= din(0);
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end if;
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when others =>
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end case;
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end if;
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end process;
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end Behavioral;
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