53 lines
1.4 KiB
VHDL
53 lines
1.4 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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entity regfile is
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Port ( outregna: in std_logic_vector(3 downto 0);
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outregda: out std_logic_vector(15 downto 0);
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outregnb: in std_logic_vector(3 downto 0);
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outregdb: out std_logic_vector(15 downto 0);
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inregn: in std_logic_vector(3 downto 0);
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inregd: in std_logic_vector(15 downto 0);
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inwe: in std_logic;
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rst : in STD_LOGIC;
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clk : in STD_LOGIC
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);
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end regfile;
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architecture Behavioral of regfile is
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component reg is
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Port ( d : in STD_LOGIC_VECTOR (15 downto 0);
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q : out STD_LOGIC_VECTOR (15 downto 0);
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rst : in STD_LOGIC;
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clk : in STD_LOGIC);
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end component;
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type regbank is array(0 to 15) of std_logic_vector(15 downto 0);
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signal regd: regbank;
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signal regq: regbank;
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begin
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regs:
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for i in 0 to 15 generate
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regx: reg port map(d => regd(i), q => regq(i), rst => rst, clk => clk);
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end generate;
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outregda <= regq(to_integer(unsigned(outregna)));
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outregdb <= regq(to_integer(unsigned(outregnb)));
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process(inregn, inregd, regq, inwe)
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begin
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for i in 0 to 15 loop
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regd(i) <= regq(i);
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if inwe = '1' then
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regd(to_integer(unsigned(inregn))) <= inregd;
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end if;
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end loop;
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end process;
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end Behavioral;
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