55 lines
971 B
VHDL
55 lines
971 B
VHDL
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-- Simple OR gate design
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library IEEE;
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use IEEE.std_logic_1164.all;
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use std.textio.all;
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entity or_test is
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end or_test;
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architecture rtl of or_test is
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component or_gate is
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port(
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a: in std_logic;
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b: in std_logic;
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q: out std_logic
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);
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end component;
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signal a_in, b_in, q_out: std_logic;
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begin
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dut: or_gate port map(a_in, b_in, q_out);
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process
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begin
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a_in <= '0';
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b_in <= '0';
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wait for 1 ns;
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assert(q_out='0') report "Fail 0/0" severity error;
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a_in <= '0';
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b_in <= '1';
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wait for 1 ns;
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assert(q_out='1') report "Fail 0/1" severity error;
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a_in <= '1';
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b_in <= 'X';
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wait for 1 ns;
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assert(q_out='1') report "Fail 1/X" severity error;
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a_in <= '1';
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b_in <= '1';
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wait for 1 ns;
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assert(q_out='1') report "Fail 1/1" severity error;
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-- Clear inputs
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a_in <= '0';
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b_in <= '0';
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assert false report "Test done." severity note;
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wait;
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end process;
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end rtl;
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