67 lines
1.4 KiB
VHDL
67 lines
1.4 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity rom_test is
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end rom_test;
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architecture rtl of rom_test is
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component clock is
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port(clk: out std_logic);
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end component;
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component dff is
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port(
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clk: in std_logic;
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rst: in std_logic;
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d: in std_logic;
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q: out std_logic
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);
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end component;
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component rom is port (
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address : in unsigned(15 downto 0);
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dataOut : out std_logic_vector(15 downto 0)
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);
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end component;
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signal clk, rst: std_logic;
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signal romout, regq: std_logic_vector(15 downto 0);
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signal addr: unsigned(15 downto 0);
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begin
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heartbeat: clock port map(clk);
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dut: rom port map(addr, romout);
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reg:
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for i in 15 downto 0 generate
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regx: dff port map(clk, rst, romout(i), regq(i));
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end generate reg;
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process(regq) begin
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addr <=unsigned(regq);
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end process;
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process
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begin
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rst <= '1';
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wait for 1 ns;
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assert(regq(0)='0') report "Fail rst" severity error;
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rst <= '0';
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wait for 10 ns;
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assert(to_integer(unsigned(regq))=2) report "Fail rom read @0" severity error;
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wait for 10 ns;
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assert(to_integer(unsigned(regq))=4) report "Fail rom read @2" severity error;
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assert false report "Test done." severity note;
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wait;
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end process;
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end rtl;
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