58 lines
1.1 KiB
VHDL
58 lines
1.1 KiB
VHDL
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity adder is
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port(
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a : in std_logic;
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b : in std_logic;
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c_in : in std_logic;
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q : out std_logic;
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c_out : out std_logic
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);
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end entity adder;
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architecture behavior of adder is
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begin
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q <= (a xor b) xor c_in;
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c_out <= (a and b) or (a and c_in) or (b and c_in);
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end architecture behavior;
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---
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity vect_adder is
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generic(SIZE: natural := 16);
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port(
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a : in std_logic_vector(SIZE-1 downto 0);
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b : in std_logic_vector(SIZE-1 downto 0);
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c_in : in std_logic;
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q : out std_logic_vector(SIZE-1 downto 0);
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c_out : out std_logic
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);
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end entity vect_adder;
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architecture behavior of vect_adder is
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component adder port(a, b, c_in: in std_logic; q, c_out: out std_logic);
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end component;
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signal carry: std_logic_vector(SIZE downto 0);
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begin
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adders:
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for i in 0 to SIZE-1 generate
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addx: adder port map(a(i), b(i), carry(i), q(i), carry(i + 1));
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end generate adders;
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carry(0) <= c_in;
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c_out <= carry(SIZE);
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end architecture behavior;
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