21 lines
359 B
VHDL
21 lines
359 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity clock is
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port ( clk: out std_logic);
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end clock;
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architecture behaviour of clock
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is
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constant clk_period : time := 10 ns;
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begin
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-- Clock process definition
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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end behaviour;
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