library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity boot_rom is
  generic
  (
    addressWidth : in positive := 16;
    busWidth : in positive := 16
  );
  port
  (
    clk: in std_logic;
    code_addr : in std_logic_vector(15 downto 0);
    code_out : out std_logic_vector(15 downto 0);

    data_addr : in std_logic_vector(15 downto 0);
    data_out : out std_logic_vector(15 downto 0)
  );
end boot_rom;

architecture Behavioral of boot_rom is
  constant alignment: positive := busWidth / 8;
  constant romsize: natural := 92;

  type romtype is array(0 to romsize - 1) of std_logic_vector(15 downto 0);
  signal romdata: romtype := (

  x"ec00",
x"9c11",
x"e28c",
x"e302",
x"3de3",
x"5e22",
x"5eee",
x"e012",
x"90c0",
x"e102",
x"1000",
x"6201",
x"e100",
x"4021",
x"5edd",
x"e012",
x"90c0",
x"e101",
x"1000",
x"6201",
x"e100",
x"4021",
x"5edd",
x"2dcf",
x"e404",
x"4cc4",
x"e11e",
x"20c0",
x"e002",
x"3de0",
x"5e11",
x"e200",
x"c200",
x"fe02",
x"e101",
x"e000",
x"c010",
x"de06",
x"10c0",
x"c000",
x"dee2",
x"e010",
x"90c0",
x"12c0",
x"2200",
x"e204",
x"3cc2",
x"1ecf",
x"2dcf",
x"e402",
x"4cc4",
x"e00e",
x"e102",
x"3de1",
x"5e00",
x"e200",
x"c200",
x"fe02",
x"e101",
x"e000",
x"c010",
x"de04",
x"c000",
x"dee6",
x"e010",
x"90c0",
x"1000",
x"e202",
x"3cc2",
x"1ecf",
x"2dcf",
x"e404",
x"4cc4",
x"e001",
x"e100",
x"c100",
x"de16",
x"e160",
x"e002",
x"3de0",
x"5e11",
x"e12e",
x"20c0",
x"e202",
x"3de2",
x"5e11",
x"c000",
x"dee2",
x"e000",
x"e104",
x"3cc1",
x"1ecf"

  );
begin

  process(clk) is
    variable code_index: natural;
    variable data_index: natural;
  begin
    if rising_edge(clk) then
    code_index := to_integer(unsigned(code_addr)) / alignment;
    if code_index < romsize then
      code_out <= romdata(code_index);
    else
      code_out <= x"0000";
    end if;

    data_index := to_integer(unsigned(data_addr)) / alignment;
     data_out <= romdata(data_index);
     end if;
  end process;

end Behavioral;
