library IEEE;
use IEEE.std_logic_1164.all;

entity adder is
  port(
        a    : in std_logic;
        b    : in std_logic;
        c_in : in std_logic;

        q     : out std_logic;
        c_out : out std_logic
      );
end entity adder;

architecture behavior of adder is

begin

  q <= (a xor b) xor c_in;
  c_out <= (a and b) or (a and c_in) or (b and c_in);

end architecture behavior;

---
library IEEE;
use IEEE.std_logic_1164.all;

entity vect_adder is
  generic(SIZE: natural := 16);
  port(
        a    : in std_logic_vector(SIZE-1 downto 0);
        b    : in std_logic_vector(SIZE-1 downto 0);
        c_in : in std_logic;

        q     : out std_logic_vector(SIZE-1 downto 0);
        c_out : out std_logic
      );
end entity vect_adder;

architecture behavior of vect_adder is

  component adder port(a, b, c_in: in std_logic; q, c_out: out std_logic);
  end component;

  signal carry: std_logic_vector(SIZE downto 0);

begin

  adders:
  for i in 0 to SIZE-1 generate
    addx: adder port map(a(i), b(i), carry(i), q(i), carry(i + 1));
  end generate adders;

  carry(0) <= c_in;
  c_out <= carry(SIZE);

end architecture behavior;
