library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;

entity vect_adder_test is
  end vect_adder_test;

architecture rtl of vect_adder_test is

  component vect_adder is
    port(
    a, b : in std_logic_vector(15 downto 0);
    c_in : in std_logic;

    q     : out std_logic_vector(15 downto 0);
    c_out : out std_logic
  );
  end component;

  signal a, b, q: std_logic_vector(15 downto 0);
  signal c_in, c_out: std_logic;

begin
  dut: vect_adder port map(a, b, c_in, q, c_out);

  process
  begin

    a <= "0000000000000001";
    b <= "0000000000000001";
    c_in <= '0';

    wait for 1 ns;
    assert(q="0000000000000010") report "Fail 1+1" severity error;
    assert(c_out='0') report "Fail carry 1+1" severity error;

    a <= "1111111111111111";
    b <= "0000000000000001";
    c_in <= '0';

    wait for 1 ns;
    assert(q="0000000000000000") report "Fail 0xffff + 1" severity error;
    assert(c_out='1') report "Fail carry 0xffff + 1" severity error;
    -- end
    assert false report "Test done." severity note;
    wait;
  end process;
end rtl;
